San Jose, Calif.--March 19, 1998--Compilogic (San Jose),developers of software that accelerate system to hardware design,introduced C2Verilog+Test, a new option for its ANSI C to Verilogcompiler, C2Verilog.
C2Verilog+Test accelerates design verification processes in thehigh-level system design of complex field programmable gate array(FPGA) and application-specific integrated circuit (ASIC) hardware.
Debuting at the IVC conference, C2Verilog+Test extendsthe capabilities of C2Verilog by allowing HDL engineers and system architects to automatically generate test benches for Verilogsimulation and design verification. Test benches compiled from C languagedescriptions can be used to verify Verilog designs created manually orcompiled by C2Verilog.
C2Verilog+Test is also useful for verifying intellectual property(IP) macros distributed as C models. Typically, these IP macros couldbe simulated only as programmable language interface (PLI) routinescalled by Verilog simulators. Although the PLI code acceleratedsoftware simulation, real hardware was required to verify the behaviorof complex systems.
With C2Verilog+Test, designers can easily compile C models intoVerilog test bench code and synthesize into a variety of hardwareemulation products. In addition to significantly accelerating thedesign verification process, the procedure also reduces the risk ofembedding IP macros in complex systems.
C2Verilog+Test is the first option in a family of specialfeatures offered by Compilogic to expand the C2Verilog product.C2Verilog+Test is priced as a $5,000 upgrade on the base C2Verilogsystem, which is priced at $9,500. C2Verilog operates in a command line mode andgraphical user interface (GUI) mode on Windows 95 and NT and in acommand mode on SunOS, Solaris, and HP-UX.
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