Boulder, Colo.--March 16, 1998--Veribest, Inc. (Boulder, Colo.) introduced Veribest 98.0A, a new software upgrade that includes enhancements to its FPGA development environment. Veribest FPGA Desktop, using Synopsys's FPGA Express v2.0.1 synthesis, now supports Actel's ACT1, ACT2, ACT3, A3200DX, and A1200XL families of devices in addition to Altera, Lucent Orca, and Xilinx devices. It also offers a new timing analyzer from Synopsys called Timetracker.
Using its extensive expertise in timing optimization for ASIC designs, Synopsys developed Timetracker to provide accurate timing in a prelayout design. The functionality of the analyzer is closely coupled with the timing constraints entered by a designer for quick identification of problematic sections of a design. The user can now optimizethe design either for area or speed, thus gaining greater flexibility and productivity in meeting the design specifications.
In addition to the timing analyzer and support for Actel devices and Actel's ACTgen macro builder, enhancements for other programmable logic vendors have also been added in Veribest 98.0A. The Xilinx v1.4 Alliance Series release, which includes Verilog and VHDL support for the XC3000 and XC5200 devices, is fully integrated in Veribest FPGADesktop. Altera LPMs are now supported in the schematic and HDL synthesis design flows, allowing the designer to efficiently handle the datapath portions of the design.
Additional enhancements to FPGA Express 2.0.1 for 98.0A include "one hot encoding" for HDL entry and an improved HDL analyzer. This increases ease of use for any customer who prototypes in FPGAs and then implements using ASICs. An improved GUI, which has been redesigned focusing on extending functionality while improving easeof use, has also been added. The result is one of the most sophisticated synthesis and optimization graphical user interfaces in the industry, supporting both the "push button" flow for the novice as well as detailed information and control for experienced synthesis users.
Veribest FPGA Desktop is a fully integrated, vendor independent FPGA design solution using FPGA Express from Synopsys and directly supporting device families from Actel, Altera, Lucent Orca, and Xilinx. Veribest FPGA Desktop supports mixed-mode design entry, graphical stimulus design, simulation, synthesis, and vendor specific placementand routing in an integrated, easy-to-use environment called Designview.
Within Veribest FPGA Desktop, a design can be entered using schematics or HDL source in any combination to match an individual design methodology. An optional graphical HDL entry methodology, offering state diagrams, flowcharts, and truth tables or state tables, can also be used in conjunction with the other methods. Both VHDL and Verilog simulation and synthesis are supported, and the integration of the vendor's place-and-route tools in Designview eliminates the need for designers to deal with format conversions and import and export of data files or back-annotation of timing values for verification.
Veribest 98.0A is now shipping. FPGA Desktop is available in different configurations with prices starting at $9,999.
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