San Jose, Calif.--March 16, 1998--Cadence Design Systems, Inc. (San Jose)introduced the Verilog-XL Desktop simulator, a lower cost version ofits industry standard Verilog-XL product. The Verilog-XL Desktop simulatoris designed to meet the capacity requirements for designing andverifying the functional building blocks of complex application-specificintegrated circuits (ASICs) and systems-on-a-chip.
The Verilog-XL Desktop software features the same quality,reliability, and functionality of Cadence's Verilog-XL Turbo simulator.This includes the complete Simvision debugging environment, as well as fulllanguage and industry standards support. A display of Verilog-XL Desktopwith the Simvision environment will be shown continuously today throughWednesday, March 18 in the Cadence Booth #507 during the International HDLConference (IVC/VIUF) at the Santa Clara Convention Center in Santa Clara,Calif.
The Verilog-XL Desktop simulator is used to design and verify functionalblocks. It supports blocks of up to 20,000 gates and 2,000 lines of registertransfer level (RTL) code. Once blocks are completed, they are then assembled into a larger, more complex system. The Verilog-XL Desktop product is completely compatible with the NC Verilog simulator from Cadence, which is required later in thedesign process for regression testing and system integration.
The Verilog-XL Desktop simulator may also be applied in the designof complex programmable logic devices (CPLDs) or field programmable gatearrays (FPGAs). These tend to be less gate intensive or need lesssimulation capacity than a typical ASIC design. With the introduction ofCadence's Desktop product, a broader range of HDL designers can now access the industry standard Verilog-XL technology and Simvision graphical debugging environment.
The Verilog-XL Desktop simulator is U.S. list priced starting at$12,000 and will be available in April 1998. It will run initially on theWindows NT platform.
Return to Headlines