Palo Alto, Calif.--May 26, 1998--Systems Science, Inc. (Palo Alto) introducedVera System Verifier (Vera-SV), a tool for verifying complete systems comprising hardware, software, and test benches.
VERA-SV provides an automated virtual prototype in which both hardwareand software verification can proceed concurrently long before the firstphysical prototype is built.
This tool can generate functional tests that mimic thetarget environment for the chip. During simulation, VERA-SV can monitor coverage points in the design and/or in the generator and use the coverage results togenerate new tests to cover untested areas.
Vera-SV consists of the base Vera-HVL verification system, plus hardware/softwarecoverification, automatic stimulus generation, dynamic coveragefeedback, data agents, and distributed simulation capability.The product supports both Verilog and VHDL. It is priced from $9,500 to $32,500, depending on the configuration.
Systems Science, Inc.
1860 Embarcadero Road, Suite 210
Palo Alto, CA 94303
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