San Jose--May 18, 1998--Cadence Design Systems, Inc. (San Jose) introducedthe Affirma software product family, which includes the new Affirma co-execution simulator, Affirma NC (Native Compiled) VHDL simulator, and Cobra cycle simulator co-execution option. The products are provided in a single co-execution environment that integrates high-speed event and cycle simulation technology, full multi-language debug capabilities, and hierarchical block- or chip-level validation techniques.
The co-execution simulator product is a heterogeneous simulation engine that optimizes both the execution of a single-language model and the concurrent execution of a mixed-language, multi-paradigm model. It delivers the full capabilities of the Cadence NC Verilog simulator and the new Affirma NC VHDL simulator with a single license. Designers can run pure Verilog, pure VHDL, or mixed Verilog and VHDL event co-execution, and additionally deploy the Cadence Cobra cycle co-execution option to mix cycle and event simulation.
The complete Cadence logic verification product line includes the Affirma co-execution simulator, the Affirma NC VHDL and NC Verilog event simulators, and the Cobra cycle simulator. The new Affirma co-execution simulator ($50,000 U.S. list price), NC-VHDL simulator ($25,000), and Cobra cycle simulator co-execution option ($20,000) begin limited production shipments in June. The NC-Verilog simulator is priced at $40,000. Existing and new users of the NC Verilog and NC VHDL simulators may upgrade to the Affirma co-execution product at any time for the option price of $10,000 and $25,000, respectively. These products are available for the industry-standard Unix-based workstations from Sun Microsystems and Hewlett-Packard.
Cadence Design Systems, Inc.
San Jose, CA
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