Pocatello, Idaho--June 29, 1998--American Microsystems, Inc.'s (AMI; Pocatello) technology roadmap for timing convergence includes a design flow thatintegrates the following three methodologies: timing-driven physical layout,clock-tree synthesis, and floor planning. Timing-driven layout has now been integrated,and floor planning is being added.
In the AMI design flow, customers synthesize the device using Synopsystools and create timing constraints and a boundary conditions file. Then AMIuses the timing constraints and boundary conditions to drivethe physical layout to optimize timing performance using Avanti'splace-and-route tools. Post placement optimizations include buffer resizingor buffer insertion to fine-tune the design timing.
Then clock tree synthesis is used to place the clock drivers. The processminimizes the skew and ensures the clock drivers are placed according to theload.
American Microsystems, Inc.
2300 Buckskin Road
Pocatello, ID 83201
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