Palo Alto, Calif.--June 29, 1998--Systems Science, Inc. (Palo Alto) announced the inclusion of the company's design tool, Powerfault-IDDQ, in STMicroelectronics, Inc.'s (Saint-Genis, France) ASIC sign-off flow.
Powerfault-IDDQ is a push-button IDDQ test solution that identifies quiet vectors through proprietary analysis capabilities, and determines the most optimal set of test vectors from multiple testbenches for maximum fault coverage. It works with standard Verilog libraries and does not require any special libraries, running in conjunction with logic simulation and working with standard Verilog simulators including Verilog-XL, VCS, and NC-Verilog. In the process of identifying "quiet" vectors, it looks for node contentions, floating, and potentially floating nodes, which are conditions that lead to reliability and power problems, frequently resulting in chip re-spins or premature failure of a chip in the field.
System Science, Inc.
1860 Embarcadero Road, Suite 210
Palo Alto, CA 94303
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