San Jose--June 29, 1998--VLSI Technology, Inc. (San Jose) said that its 0.25-m (drawn gate length; 0.18-m Leff) VSC9 custom circuit process technology has passed its qualification requirements in its San Antonio fab line and is in full production .
At the same time, the company announced that development of its VSC10 0.2-m (drawn gate length; 0.15-m Leff) process is on schedule, with full production qualification expected in early Q4 1998. The company also committed itself to offering copper-based interconnect technology as an option on its forthcoming VSC11 0.15-m (drawn gate length) process technology generation.
Based on extensive simulation of circuit performance, VLSI sees copper interconnect as providing performance advantages for relatively long interblock connections at nanometer process generations. VLSI plans to deploy copper for the upper layers of interconnect (Metal 4 and Metal 5) of its next-generation VSC11 process, which will come on-line in 1999.
VLSI plans to release full details of its VSC11 deep-submicron custom silicon manufacturing process this autumn, including a full development schedule.
Dipu Pramanik, director of process technology
VLSI Technology, Inc.
San Jose, CA
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