Beaverton, Ore.--June 15, 1998--Summit Design, Inc. (Beaverton) announced the immediate availability of Dasys's Rapidpath Version 3.2. Summit acquired exclusive distribution rights to all products from Dasys, Inc. (Pittsburgh) last fall.
Rapidpath lets users enter behavioral level designs in VHDL or Verilog and automatically synthesizes RTL code, which then feeds into the standard RTL synthesis design flow. Behavioral design reduces coding effort by up to 10 times over straight RTL coding for large, complex designs.
The tool supports interactive and incremental scheduling. In addition, the user can interactively specify resource and/or timing constraints to explore area and performance tradeoffs. Design teams can take advantage of the overall productivity gains to either perform more design exploration or reduce time to market.
Rapidpath incorporates implementation issues into the behavioral synthesis process. Interconnects are considered up front in the design flow via wire load models and datapath partitioning. The tool automatically outputs both logical and physical partitions, including separate memory, control, and datapath elements for downstream implementation tools. Standard Verilog or VHDL code is produced.
Rapidpath V3.2 includes new user interface features, including a graphic timing display and design flow manger. To provide graphical capture of behavioral code and display of RTL finite state machines, the tool is being integrated with Summit Design's Visual HDL.
Rapidpath is available immediately through Summit's worldwide sales channel for $95,000 per floating license. Platform support includes Sun SPARC running SunOS or Solaris, or HP PA-RISC running HP-UX. Supported RTL synthesis tools are Synopsys' Design Compiler and Exemplar Logic's Leonardo.
Summit Design, Inc.
9305 S.W. Gemini Drive
Beaverton, OR 97008
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