Beaverton, Ore.--June 15, 1998--Summit Design, Inc. (Beaverton, Ore.) announced its Virtual-CPU hardware/software co-verification tool now fully supports IBM's PowerPC processor cores. Embedded systems designers using IBM cores and System-on-a-Chip (SOC) designers can now take advantage of the full power and feature set of V-CPU for hardware/software co-verification.
V-CPU provides embedded designers with a virtual environment for debugging their software and hardware. V-CPU allows hardware and software designers to use the IBM core master and slave bus models with the IBM PVS instruction set simulator and software debug tools integrated with their favorite HDL logic simulator.
V-CPU has been tightly linked with the PowerPC 401 family of cores and the PLB and OP macro libraries, which consist of processor local bus, on-chip peripheral bus, device control register bus architectures and PLB master and slave macros used in Core+ASIC development and SoC designs. These IBM-provided and verified models are now available for both software verification and C-based verification test benches.
Under this agreement Summit has licensed IBM's core-based Verilog and VHDL bus models and its Power Visual Simulator (PVS), both of which will be packaged and distributed with V-CPU.
PVS is an instruction-level simulator for the PowerPC architecture with an integrated high-function graphical user interface. The PVS simulator presents a software view of the PowerPC architecture. It models the PowerPC instruction set, register space and memory space. It also models most elements of the PowerPC operating environment architecture such as effective-to-virtual-to-real address translation, interrupts and processor-specific registers. It provides very high-speed instruction execution with usability that includes a 'C' source level debugger.
Summit Design, Inc.
9305 SW Gemini Drive
Beaverton, OR 97008
IBM Microelectronics Division
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