North Billerica, Mass.--June 15, 1998--Chrysalis Symbolic Design, Inc. (North Billerica) announced that they will develop a formal verification flow for Advanced RISC Machines, Ltd.'s (Cambridge, U.K.) new synthesized version of the ARM7TDMI core, the ARM7TDMI-S core using their Design Verifyer.After RTL verification, to make sure that the core functions correctly with the rest of the chip, it is necessary to check that no changes to the core's functionality were inadvertently introduced by any of the subsequent implementation steps such as synthesis, test or layout.Equivalence checking is the methodology of choice for many users today for gate level functional verification. Using equivalence checking, users are able to prove that the gate level netlists or layout netlists correctly implement the original RTL. In the case of a third-party IP core such as the ARM7TDMI-S, the user can prove the gate level implementation of the core matches the RTL.
Chrysalis Symbolic Design, Inc.
North Billerica, MA
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