San Jose--June 18, 1998--Siquest, Inc. (San Jose) has developed proprietary software enabling remapping of FPGA netlists into their gate array equivalents without requiring that customers generate test vectors. The new Full Scan FPGA conversion program was developed at the Siquest Design Center in San Jose. Engineering turn time is one to two days for conversions of up to 40,000 gates.
The Full Scan method of scan insertion is designed to generate test vectors automatically without altering the functionality of customer net lists. Fault coverage is claimed to be 99.6 percent. Rework is rarely required and 'first-time-right silicon' is virtually assured.
The software is fully optimized for the Siquest 0.8-m CMOS gate array library and soon-to-be-released 0.5-m library.
Siquest's ASICs are designed to plug and play exactly like the FPGAs they replace. Pin outs are identical to the original FPGA and Full-Scan implementation is transparent, adding 14 percent to average gate count, compared with the 30 percent achieved with previous scanning methods.
San Jose, CA
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