San Francisco--June 15, 1998--Mentor Graphics Corp. (Wilsonville, Ore.)unveiled OLA capabilities for its design-for-test (DFT) andgate-level ASIC static timing technology. System designers will use the DFT and static timing analysis tools on all commonlycompiled libraries.
Systems designers need only obtain a singlelibrary to drive the majority of the design process. Likewise, ASIC vendorsneed to support just a single library format to work with all EDA tools. MentorGraphics is scheduled to supply versions of its DFT and ASIC static timinganalysis tools for qualification with ASIC companies' production libraries bythe end of 1998.
Products being previewed include Fastscan for full-scanand structured partial-scan automatic test pattern generation (ATPG),DFTAdvisor for test analysis and synthesis, and SST Velocity, an ASIC static timing analysis tool.
A long-term, common ASIC library format can be utilized by EDA vendors,silicon vendors and ASIC manufacturers. Advantages of a common library formatinclude increased flexibility during product design and increased verificationcapabilities. Systems engineers using these tools will be able to automatically read allASIC models supporting the OLA standard, eliminating the time and costassociated with supporting proprietary library formats to executemanufacturing tests and static timing analyses.
OLA libraries are based on the existing Delay Calculation Language (DCL)and API, as well as the Advanced Library Format (ALF). In April 1997, Mentor Graphics released the library format used by its DFTtool suite for use in Open Verilog International's development of the ALFstandard for ASIC library modeling formats. Other applications relying onfunctional information, such as cycle-based simulation, formal verification,emulation, power analysis and synthesis, can employ this format.
Mentor Graphics Corp.
8005 S.W. Boeckman Road
Wilsonville, OR 97070-7777
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