Norwood, Mass.--June 22, 1998--Analog Devices, Inc. (Norwood) unveiled its next generation of Sharc digital signal processors (DSPs). The family features a 32-bit general purpose DSP architecture, calculating more than one billion math operations per second on both fixed-point (32-bit) and floating-point (32- and 40-bit) data types.
The new ADSP-21100 SHARC family has a microprocessor architecture called Single Instruction Multiple Data (SIMD) The SIMD SHARC adds a second set of computational units (arithmetic and logic unit, barrel shifter, data register file, and multiplier) while maintaining a simple programming model and minimizing code size. With the SIMD SHARC, ADI has accelerated memory bus bandwidth to 1600 megabytes per second, added two 64-bit data buses, and increased the number of 80-bit accumulators for fixed-point operations to four.
All totaled, the new SHARC DSP executes a 1024-point, bit-reversed, complex FFT (Fast Fourier Transform) in 46 microseconds. The new family is code compatible with ADI's popular ADSP-2106x SHARC DSPs. It is supported by ADI's VisualDSP hardware and software development system. In addition, ADI and Ixthos, Inc. (Leesburg, Va.) are jointly developing a software library of ready-to-use algorithms.
ADI's VisualDSP Release 4.0 development tools support the new ADSP-21100 family and are available now. Samples of the ADSP-21160 will be available through ADI in the fourth quarter of 1998 at a sample price of $300.
Analog Devices, Inc.
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