San Jose--July 27, 1998--Cadence Design Systems, Inc.(San Jose) announced a new, multi-tool timing-driven design flow thataddresses the remaining technical obstacles preventing the widespread adoptionof timing-driven physical implementation methodologies for deep-submicrondesigns. The patented approach combines a new method of constraintpassing with timing-driven design planning, placement and routing, andphysical optimization algorithms.
This new approach, the Cadence System-Level Constraint Timing-DrivenDesign Flow, delivers up to 20percent faster clocks and as much as 6X improvement in design turnaroundtimes, with substantially smaller memory and disk-space requirements, inearly trials with NEC and other customers. Design teams at these companiesare routinely achieving first-pass timing closure for complex 0.35-m (andbelow) process designs.
The Design Flow uses system-level constraints, specified by the designer in the industry-open,general constraint format (GCF), to represent chip and block-level timingthroughout the flow. Cadence has patented a set of "stage-based" algorithmsthat are generated by Pearl, its embedded timing analysis engine, and thenread, analyzed, and acted upon by each tool in the flow-design planning,place and route, physical optimization, extraction, and clock-tree design. This process ensures that consistent and complete timing information is available at eachstep of the design.
To accelerate the adoption of the Design Flow within customer environments, Cadence ConsultingServices offers a range of education, flow, and methodology transitionservices tailored to the design approach. The Design Flow is available now.
Cadence Design Systems, Inc.
San Jose, CA
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