Hillsboro, Ore.--July 27, 1998--Lattice Semiconductor Corp. (Hillsboro) announced the shipment of Lattice's new ISPHDL System for Synplicity for high-density ISP device design. The system features Synplicity's Synplify VHDL and Verilog-HDL synthesis offerings integrated with Lattice's ISPDS+ HDL Synthesis-Optimized Logic Fitter v5.2 for high-density ISP device design.
The Synplify synthesis tool features the company's B.E.S.T. algorithms. The tool accepts Verilog and VHDL descriptions and produces optimized implementations for programmable devices from many vendors. It contains a multi-level timing constraints management system. It also includes a built-in language-sensitive editor and an optional graphical (block diagram) analysis tool that gives direct feedback for design debug, specifically designed to simplify the transition to HDL-based design methodology. Synplify is combined with the Lattice ISPDS+ HDL Synthesis-Optimized Logic Fitter version 5.2 and ISPdownload in-system programming utilities.
The ISPDS+ fitter has been designed for tight integration with the Synplify front end, while supplying interfaces for back annotation and post-route simulation with many CAE vendor tools. Also added is new device support, including ISPLSI 3320 and ISPLSI 3448.
The ISPanalyzer tool, designed to simplify in-system debugging, allows designers to probe internal registers and nodes non-invasively. It provides the ability to connect a buried node to output pins without repeating design entry, fitting, and verification steps. Users can manipulate the compiler output, changing only the routing paths of the desired internal nodes, while preserving the original implementation of the design. The compilation process generates the list of observable nodes and the pins to which the nodes can be connected. The graphical user interface for the ISPanalyzer tool provides access to the information, so users can select specific buried nodes for connection to device pins for easier debugging.
The new ISPHDL System for Synplicity is supported on a PC platform and has a list price of $995 for the base system version that supports Lattice's ISPLSI 1000E, 2000, 2000V, and 3000 device families. For an additional $2,500, users can upgrade to the unlimited capacity advanced system version that supports Lattice's ISPLSI 6000 family. Both systems are available now.
Tim Schnettler, Design Tools Marketing Manager
Lattice Semiconductor Corp.
5555 NE Moore Court
Hillsboro, OR 97124
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