Santa Clara, Calif.--July 27, 1998--VHDL International (VI; Santa Clara) announced that the VHDL register-transfer level (RTL) Synthesis Standard, known as IEEE 1076.6 and based on existing standards IEEE 1076 and 1164, has passed IEEE balloting. It will serve as a standard syntax and semantics for VHDL-based RTL synthesis to maximize design reuse and provide a foundation for synthesis and verification of synthesized designs.
A total of 115 people participated in the ballot, with 90 ballots returned. Of those 90 ballots, 88 percent voted to approve the standard. Over the next few weeks, the IEEE Ballot Resolution Committee will review comments noted during balloting.
Begun in 1996 under the sponsorship of VHDL International, the RTL Synthesis standardization effort was undertaken to address the need for a more portable and reusable design specification for use by the entire EDA industry: designers, EDA tool suppliers, IP providers, and ASIC companies. The work was transferred to the Design Automation Standards Committee (DASC) of the IEEE, once initial industry consensus was achieved and feasibility proven.
The group, under the auspices of VI and the Industry Council Project Technical Advisory Board (IC PTAB) developed the documentation presented to the IEEE for consideration as a standard. The document is based on inputs from Cadence Design Systems, IBM, Mentor Graphics, Synopsys, and the European Synthesis Working Group.
The VHDL RTL Synthesis Standard can be viewed or downloaded from www.vhdl.org/siwg.
Santa Clara, CA
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