Wilsonville, Ore.--July 13, 1998--Mentor Graphics Corp.(Wilsonville) announced DFM (design for manufacturability)Silicon Partners, a program aimed at customers of major chip foundries to achieve greater yield and higher performance from complexintegrated circuits (ICs). The program aims to cutchip development time by as much as six months.
Through DFM Silicon Partners, foundries and Mentor Graphics collaborate todeliver silicon-calibrated technology files and models to support mutualcustomers who use Mentor Graphics' deep-submicron verification andinterconnect solutions, including Calibre, xCalibre, Mach TA, andadditional tools.
The initial version of the DFM Silicon Partners test chip includes a focuson deep submicron parasitic extraction.
The test chip initiative is based on advanced interconnect test chipdesign, measurement, and RC extraction tool calibration work from MentorGraphics and BTA Technology, with support from Adaptec and severaldeep-submicron foundries and research labs. It allows silicon verification ofinterconnect capacitance down to 0.01fF.
Mentor Graphics' team of DFM experts will enhance the test chip toanticipate silicon demands as well as the silicon modelingrequirements of upgraded deep submicron tools, including such areas asanalog/mixed-signal and optical proximity correction.
Mentor Graphics Corp.
8005 S.W. Boeckman Road
Wilsonville, OR 97070-7777
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