San Jose--July 13, 1998--Altera Corp. (San Jose)announced the availability of the EPM7256A, from the Max 7000A family. The EPM7256A offerspin-to-pin speeds as fast as 7.5 ns.
Designed using Altera's second-generation Multiple Array Matrix (Max)architecture, the CMOS EEPROM-based device features 16logic array blocks, 164 I/O pins, and up to 5,000 usable gates.
The product features Altera's patented Multivolt interface that enablesI/O support of 5.0-V, 3.3-V, and 2.5-V interface voltage levels, andin-system programmability (ISP) with support of the Jam programming andtest language. It is a true 3.3-V CPLD fabricated using a 0.35-mprocess.
The EPM7256A is supported by Altera'sMax+Plus II development system for PC and workstation platforms. Thesoftware offers an architecture-independent developmentenvironment, which enables the designer to target designs to any of Altera'sdevice families. It provides integration withtools from Cadence, Mentor Graphics, Synopsys, Viewlogic, and otherEDA vendors.
The EPM7256A is available now in a 208-pin PQFP package and is expected tosoon be available in 100-pin TQFP and 144-pin TQFP, as well as Altera's newFineline BGA packages. Volume pricing for the EPM7256A is projected to be$15.50 by the end of 1998 in 25,000-unit quantities.
San Jose, CA
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