Milpitas, Calif.--Oct. 27, 1998--Two highly-configurable cores that enable designers to create system-level ASICs with the industry-standard universal system bus (USB) interface were introduced by LSI Logic (Milpitas) as part of the company's Coreware library. A new Host Core allows the connection of USB-enabled peripherals to embedded system platforms, and a new Hub Core provides the ability to expand the number of USB connections in host-attached peripherals.
The two new cores complement a previously introduced USB Coreware component, a Function Core that provides the USB interface for peripheral devices such as printers and scanners. The now complete USB core family will enable designers to develop system-level ASICs with USB peripheral connectivity for embedded systems addressing consumer applications such as telephony, digital cameras, as well as handheld computers.
The Host, Hub and Function cores are fully USB compliant. Provided in highly configurable architectures, the cores can be modified to meet specific customer requirements. Each core is offered in a "firm" implementation as a fixed netlist with layout and timing guidelines. This approach provides ample flexibility, allowing the physical design layout to be easily modified while maintaining USB functionality and timing closure. LSI Logic also offers USB transceivers in the I/O libraries. Fully compliant to the USB specification, the transceivers operate in both full- and low-speed modes, enabling fully- integrated single-chip systems.
To simplify design integration, the cores are provided in both encrypted RTL and unencrypted SCAN-inserted netlist forms. RTL speeds the development of the system ASIC architecture at the behavior simulation level, while the netlist accelerates the structural implementation. With an optimized, proven, fixed netlist in LSI Logic's ASIC technology, designers can concentrate on other value-added aspects of the system ASIC. By using these RTL and netlist formats, the development and prototyping of a large system-on-a-chip design incorporating USB, MIPS, PCI, and Ethernet cores was completed in less than a year from design conception.
The OHCI- and USB -compliant Host Core connects USB-enabled peripherals to a host system. It generates and manages the Universal Serial Bus host interface and establishes communications between the host system and USB peripherals and is configurable to support from 1 to 15 root hub ports. The Host Core can be integrated into core logic for workstations and PCs and a wide variety of embedded systems such as set-top boxes and Windows CE-based palm-size and handheld personal computers.
Designers configure the core by answering a series of questions presented in a configuration utility, which generates synthesizable RTL based from the designer input. The Host Core's default configuration provides two Root Hub ports; however, it can be configured to support up 15 root hub ports.
The Hub Core provides the critical ability to add peripherals to USB-enabled systems and detect connections and removals. It can be configured to support from 1 to 15 downstream ports for use with both low- and full-speed peripheral devices. The Hub Core typically will be used with high-end printers, multifunction peripherals, CRT monitors, and flat-panel displays.
The default design supports four ports however it can be configured to support from 1-15 ports. Designers configure the Hub Core through a configuration utility, which generates synthesizable RTL from a worksheet completed by the designer.
The USB cores are available now in the Coreware library. They are priced only in the context of a complete Coreware system-on-a-chip design, not as an individual core or component.
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