Henderson, Nev.--March 29, 1999--Aldec, Inc. (Henderson) has announced therelease of a new Block Diagram Editor. The new technology offers greaterflexibility and support for mixed-HDL designs of complex FPGA, CPLD, orASIC devices using HDL modules, cores, or predefined LPM macros.
The Block Diagram Editor allows the user to mix all design descriptionmethods in a single project using VHDL source code, state diagrams, andblock diagrams. Multilevel, hierarchical designs can be clearly defined andeasily updated and maintained. Graphical symbols for all user andsystem-level library components are automatically generated and updated toreflect any changes made at the source level. The new Block Diagram Editoralso includes editing features that allow designers to assign anyarchitecture to an empty module and rotate, mirror, or push into that blockto change the layout and interface.
The Editor allows the user to quickly draw the structure of an HDL designand generate VHDL source code that can be used for Logic Synthesis or VHDLsimulation. It automatically generates optimized VHDL source code forExemplar's, Synopsys's, and Synplicity's logic synthesis tools. Additionalediting to the source code can be preformed directly in Aldec's designenvironment once the code has been generated. Compared with standard textentry, which is also prone to errors, automatic code generation improvesthe overall design speed.
The advanced Design Rule Checking (DRC) function offered in Block DiagramEditor allows the user to verify that the graphical blocks and connectionsbetween them are valid before the VHDL source code is generated. A 'CompareSymbol with Contents' option automatically checks all ports and generics toensure the integrity of a component for users that manually change VHDLsource code at the text level. All DRC functions can be customized toprovide the user complete control over design errors and warningmessages.
The new Editor allows for a team of design engineers to create and utilizeseparate HDL modules, cores, and LPM macros in the development of ahigh-density IC device. The graphical block illustrates all simple orcomplex inputs and outputs that can be defined in VHDL. The editor alsosupports FPGA vendor specific macro generators from Actel, Altera, Lucent,and Xilinx. A symbol will automatically be generated for any IP orpredefined macro attached to the project. The designer is able to push intothe symbol and view or edit the source code directly from the HDL designenvironment.
The new Block Diagram Editor will be packaged and shipped in Active-HDLversion 3.5. The initial release of the product will support VHDL sourcecode generation; Verilog is to be added in the next release currentlyscheduled for Q2 1999. Active-HDL starts at $3,600. A free evaluationversion can be obtained by consulting the Web site or dialing the toll-freenumber.
Return to Headlines