San Jose--April 28, 1999--Atmel Corp. (San Jose) and Synplicity, Inc. (Sunnyvale, Calif.) announced support betweenAtmel's AT40K FPGA version 6.0 development software and Synplicity's Synplify logicsynthesis tool.
Atmel's patented AT40K FPGA architecture supports high performance DSP-based designs by using acombination of its DSP optimized core cell and on-chip diagonal connections. The AT40K FPGAsfeatures are exploited by the Synplify software through technology mapping of HDL-baseddesigns directly into the AT40K core cell structure. In addition, the Synplify softwareidentifies logic structures and passes system block requirements to Atmel's macro generatorsoftware tools, exploiting the full capabilities AT40K architecture.
Atmel's FPGA Designer 6.0 will be provided at no charge to qualified Synplicity users. This willallow existing users to target designs to Atmel' s AT40K, Xilinx pin compatible FPGAs withFreeRAM.
FOPGA Designer 6.0 is available free of charge to other qualified designers for a limited time viaAtmel at: www.atmel.com/fpga_software.html.
The FPGA Designer 6.0 incorporates a suite of industry-standard design tools including HDL Planner,netlist import, technology mapping, multi-chip partitioning, automatic logic and RAM compilers,timing-driven automatic placement and routing, interactive timing analysis, and bitstream generation andutilities.
The AT40K is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10 nsprogrammable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, cache logicability (partially or fully reconfigurable without loss of data), automatic component generators, and rangein size from 5,000 to 150,000 usable gates. I/O counts range from 128 to 384 in industry-standardpackages ranging from 84-pin PLCC to 475-pin PGA, and support 3V and 5V designs.
Synplicity's Synplify synthesis tool represents a breed of synthesis toolsdesigned independent of existing academic or commercial code and features the company's B.E.S.T. algorithms. The tool accepts industry-standard Verilog and VHDL descriptions andproduces optimized implementations for programmable devices from many vendors.
The recent release of Synplify 5.0 contains a unique multi-level timing constraints management system,giving designers the most accurate automated solution combined with the most robustuser-controlled features, providing designers flexibility in the way they use their synthesis tool. Designedto deliver the highest quality of results, Synplify is also extremely fast and easy-to-use. It includes abuilt-in language-sensitive editor and optional graphical (block diagram) analysis tool that gives directfeedback for fast design debug.
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