San Jose--June 28, 1999--Xilinx, Inc. (San Jose) announcedthe availability of the Webpack suite--a new, integrated design environment specifically tailoredfor the XC9500 CPLD series. This suite of tools, is a collection of three free, downloadable modules:VHDL, Verilog, and ABEL synthesis; device fitter tools; and device programming. Eachmodule may be used separately with existing EDA tools or used in combination to create an integratedCPLD environment. This approach offers engineers complete flexibility when designing with Xilinx.
In addition, Xilinx also announced a new release of its Webfitter product. Thison-line CPLD evaluation system now includes a new release of ABEL, version 7.1, additional synthesistechnology, and on-line price quotes.
Both the Webfitter and the Webpack tools incorporate technology acquired from Minc+Synario.Xilinx has made several key updates to both the project navigator and ABEL and has introduced XilinxSynthesis Technology product specifically for the XC9500 CPLD series. Enhancements to the ABELlanguage focused on improved design flows and overall reliability.
Xilinx is also working with third parties to allow EDA and other programmable logic suppliers tolicense the latest version of ABEL, v7.1 via the OEM channel. The ABEL language is still a widely usedHDL for CPLDs and simple PLDs such as PALs and GALs. With respect to that, Xilinx is creating anOpenABEL consortium that will govern the direction and enhancement of the ABEL language. Xilinxwill place ABEL into the OEM channel and create the OpenABEL consortium later this year.
Xilinx offers three distinct downloadable modules. The XC9500 HDL-ABEL Synthesis Tools module,enhanced specifically for the XC9500 series, incorporates a projectnavigation system with the updated version of ABEL, coupled with VHDL and Verilog synthesis (XST).The XC9500 Device Fitter Tools module includes the Xilinx implementation tools for CPLD deviceoptimization and timing driven fitting. This set of tools can run with existing synthesis and schematiccapture tools or can be implemented from within the Webpack synthesis and ABEL environment. Thismodule also includes the Constraints Editor, Interactive Timing Analyzer, and new CPLD Chipviewertools. The Device Programming Tools module contains programming software that allows for full IEEE1149.1 JTAG programming on any Xilinx CPLD or FPGA.
The Webfitter tool allows designers to submit any VHDL, Verilog, ABEL, EDIF or XNF file for anevaluation within minutes. The Webfitter tool will also accept input from other programmable logicvendors. Users can target their design specifically by density, package, speed, and voltage or chooseautomatic device selection. Users can peruse the utilization and timing reports, view data sheets, and getinstant price quotes on-line. For further verification, the Webfitter tool provides HDL timingsimulation models as well as a JEDEC programming file. All of the reports, timing models, and deviceand programming files are available for immediate download.
The Webfitter tool is available on-line at www.xilinx.com/sxpresso/webfitter.htm. The Webpacksuite is available for immediate download at www.xilinx.com/sxpresso/webpack.htm.
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