Hillsboro, Ore.--July 26, 1999--Lattice Semiconductor Corp. (Hillsboro) released the first of a familyof 3.3- volt in-system programmable digital crosspoint devices.
The ispGDX160V is the first member of the new ispGDXV family. The ispGDXV architecture is a functional superset of the earlier5-volt ispGDX family with new features, higher I/O options, and a 3.3-volt logic core. The ispGDXV family offers a newprogrammable MUX width for MUX chaining and supports up to 16:1 real-time multiplexing. The family supports I/O densities from 80 up to 240 and includes other features such as a bus hold latch perI/O, programmable clock enable logic, hot socketing tolerance, output slew rate control, and full boundary scan test and in-systemprogramming support (IEEE 1149.1-compliant).
The logic architecture of the ispGDX160V features 160 programmable I/O cells interconnected by a Global Routing Pool (GRP)that input-to-output signal delays (Tpd) of 5ns, clock-to-output delays (Tgco) of 5ns, and pin-to-pinoperating frequencies (Fmax) of 111 MHz. It is offered in advanced 208- and 272-ball BGA packages as well as a 208-pin PQFP(plastic quad flat pack) package. The ispGDX160V is available in both commercial and industrial operating ranges.
This new device is optimized for digital signal interface and routing applications, and represents a new classof high-density programmable components distinct from CPLDs and FPGAs that supports board-level rather than chip-level logic interface solutions.
The 5ns speed grade ispGDX160V in the 208 ball BGA package is available now and priced at $9.95 in high volume quantities.
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