SUNNYVALE, Calif. Virage Logic Corp. will develop memory compilers based on the single-transistor SRAM technology of embedded-memory vendor MoSys Inc. The fourth-generation Custom-Touch compilers are being designed expressly for use with the 0.18- and 0.15-micron standard logic processes of Taiwan Semiconductor Manufacturing Co. (TSMC).
According to the companies, these memory compilers enable system designers requiring ultra-dense memory to easily embed large quantities of cost-effective memory in their designs.
By combining the Custom-Touch compiler technology of Virage Logic with the 1T-SRAM memory technology of MoSys, customers will be able to rapidly generate the high-capacity memory configuration of their choice at any stage of the design cycle, said the companies.
The compilers are said to facilitate "what-if" analysis and performance trade-off decisions early in the design cycle.
According to the companies, a template generation mechanism for EDA models will allow users to choose from many popular design flows and ensure that all the necessary information is automatically generated for integrating and verifying the memories.
Additionally, Virage's compiler development process subjects all released products to rigorous testing as part of the company's FirstPass-Silicon program.
TSMC will manufacture the test chips for these compilers, and Virage and MoSys will test and evaluate the Custom-Touch 1T-SRAM compiled results in silicon. This, according to the companies, will reassure customers that their compiled memories will work in silicon.
The first Custom-Touch 1T-SRAM compiler is scheduled for release in the second quarter.