BERKELEY, Calif. A multi-university collaborative research effort is quietly laying the groundwork for a revolution in chip design and EDA software. With a 10-year research horizon, the Gigascale Silicon Research Center (GSRC) here is looking at some very unconventional ways to put a billion transistors on a chip.
The GSRC is portraying a future in which masked ASICs as we know them may not exist one where a new EDA industry homes in on programmable systems while designers assemble 50,000-gate blocks as easily as they do 50-gate macrocells today. At the root of virtually all the GSRC projects is one potent idea: platform-based design, in which predefined architectures allow rapid creation of application-specific derivatives.
"The problem we are presented with is to solve the productivity gap," said Richard Newton, the GSRC's director and a professor of electrical engineering and computer science at the University of California at Berkeley. "That problem is impossible to solve. We have to change it to a different problem that we can solve, and that means we have to change the methodology of how we design circuits."
Poised to enter its second year of existence and armed with broad industry support, the GSRC is one of two Focus Center Research Programs established under the multi-university Marco program. (The other is the Interconnect Consortium, led by Georgia Tech.) The GSRC has $10 million in funding for the first two years, contributed by the Semiconductor Industry Association, Semiconductor Equipment and Materials International (SEMI) with the Sematech manufacturing consortium, and the Department of Defense.
Led by UC Berkeley, the GSRC involves faculty and dozens of researchers from nine other universities. Indeed, one thing that's unique about this program is the breadth of the collaboration.
"Faculty have tended to build autonomous research empires," said Kurt Keutzer, professor of electrical engineering and computer science at Berkeley and GSRC's associate director. "As a result, professors are often working on the wrong problem, and research is incomplete. GSRC is very much about trying to turn around this state of affairs."
Significantly, the GSRC's scope is expansive, encompassing everything from system-level design to laying transistors on silicon. The project is even looking at the design of silicon itself its "fabrics," or basic building blocks in addition to EDA software and design methodologies.
Another distinctive aspect is broad involvement from industry. Companies like Applied Materials, IBM, Intel, Lucent, Synopsys and Texas Instruments are involved on the executive advisory group, and the technical advisory group includes representatives from Cadence, LSI Logic, IBM, Intel, Motorola, Synopsys and Texas Instruments.
"I think GSRC is a pretty big deal," said Albert Yu, senior vice president and general manager of Intel Corp.'s microprocessor group and a member of the executive advisory group. "Part of the reason I was interested in participating is that they were quite receptive to our inputs." Yu said that Intel, which has a large R&D effort of its own, has assigned several people to participate full-time in GSRC research.
"I think what Richard Newton has pioneered is really a new look at where design methodologies are going," said Aart de Geus, chief executive officer of Synopsys Inc. and another member of the executive advisory group. "We are participating actively in trying to set directions for this group."
"A new design flow is emerging that goes from system concepts all the way to silicon," said Patrick Scaglia, vice president for research at Cadence Laboratories and a member of the technical advisory group. "If we can get a consensus on the best design flow over the next 10 years, that by itself is going to have a huge impact."
Seeking its own consensus, the GSRC has radically redesigned itself in its first year of operation. The center started with a stated goal to "rebuild the RTL foundation." But that focus changed as researchers became aware of the implications of platform-based design.
"It became clear that the bottom line was not rebuilding the RTL [register-transfer level] foundation, but one-pass, predictable implementation from a microarchitecture," Newton said. "Microprocessor-level performance on an ASIC schedule is one of our goals."
Following an early 1999 meeting in which Newton invited researchers to present "a crazy, compelling idea," the GSRC effort coalesced around four broad themes: component and communication-based design; fully programmable, platform-based systems; "constructive fabrics," or on-the-fly synthesis and assembly of soft intellectual-property (IP) blocks; and tools and metrics for ensuring quality in EDA software.
All that research is aiming at an ambitious goal: billion-transistor chips in 50-nanometer technology, using digital and mixed-signal IP from various sources and running as fast as 10 GHz. The group expects such chips will be designed with less than 30 designers in under six months-all while keeping an eye on cost, timing and power constraints.
In a recent annual review held at the offices of Cadence Design Systems, Keutzer noted that the GSRC made some key discoveries in its first year: that a global synchronous model no longer works; that managing concurrency and parallelism is important at every level; and that designs will be heterogenous, mixed-signal, component-based implementations.
Keutzer acknowledged, however, that many unresolved technical issues remain. And Newton said that funding cuts have caused some "pretty tough paring back" of GSRC's intent to do advanced, original circuit design.
Partially compensating for those shortcomings is an alliance with the Berkeley Wireless Research Center, a university-led project that seeks to define the next generation of wireless communications.
It's no surprise that Alberto Sangiovanni-Vincentelli, professor of electrical engineering and computer science at UC Berkeley, is leading the GSRC's "communications and component-based design" theme. Sangiovanni-Vincentelli is largely responsible for articulating the concept of platform-based design upon which that theme is based.
Sangiovanni-Vincentelli cited research showing that mask-making costs are going up to $1.5 million in the next generation and may eventually hit $10 million per chip design. "It's clear from these prices that you cannot afford to have ASICs as you think of them today," he said. "That's why there's a thrust toward platform-based design."
Platform-based design is built upon families of architectures that use reconfigurable hardware blocks and programmable software blocks. A very strong methodology is needed for plugging in these parameterizable components.
From that need, said Sangiovanni-Vincentelli, comes the idea of communication and component-based design, and the mandate for a clear separation between behavior and microarchitecture.
"What we're trying to accomplish is developing a design methodology that can include synthesis and formal verification and that can speed up the design process by orders of magnitude by being able to reuse components," he said. At the highest level of abstraction, he noted, concurrency is turning out to be the most important issue.
"One major concern in research is to try to resolve the concurrency issue by working with models of computation," said Sangiovanni-Vincentelli. "We need a formal way to make sure, when you put together components, you don't get into problems like deadlock."
Part of that effort involves the semantics project that the GSRC has undertaken with the System-Level Design Language committee. Here, the intent is to define an "abstract syntax" upon which different languages can be based.
"Models of computation are what semantics are all about," noted Sangiovanni-Vincentelli.
Another project in the communication/component design theme has to do with bus protocol verification. That research is looking for a consistent way to specify buses so that they can be formally verified. Thus far, researchers have determined that a monitor-based approach-one that uses state machines to track past and current conditions-is a promising direction.
A third project is looking at protocol design and synthesis. That project attempts to automatically generate interfaces that can handle communi-cations between components that require different protocols.
To put its concepts to the test, the communication/component design theme has adopted the Berkeley Wireless Research Center's PicoRadio low-power wireless chip as a design driver.
"In four man-months, we were able to capture the design of protocols very quickly and evaluate different architectures," said Berkeley's Sangiovanni-Vincentelli.
In addition, he pointed out, a group of students came up with a "very novel way of thinking about wireless communications" with a multihopping approach involving cell-to-cell communications.
Perhaps the most extreme view of platform-based design is one in which there is no custom hardware design at all. The system-on-chip is differentiated through embedded software and through programmable hardware such as FPGA logic. That's the topic of the "fully programmable systems" theme headed up by Keutzer.
"I really think that fully programmable systems for application-specific parts will begin to chomp away at a significant part of the ASIC market," Keutzer said. Working with such devices, he said, will be much less like synthesis and much more like programming an application-specific processor.
For that reason, Keutzer sees the EDA industry splitting into two parts. The "traditional" EDA industry, which is focused on hardware design, will become more like the semiconductor equipment industry, and its offerings will be part of equipping a fab. A new "desktop" EDA industry will sell tools such as software estimators, performance visualizers, schedulers, compilers and debuggers.
The latter may sound like today's embedded-software development industry, but Keutzer's group is not talking about standard Intel processors. Rather, it envisions huge chips that might place as many as 64 processors on one die.
Research under this GSRC theme is focusing on developing a "programmer's model" and a software development environment that allows an efficient implementation into a fully programmable architecture. Of the two, the programmer's model is the more important, said Keutzer. The model must provide an efficient way to write programs for complex, very long instruction word (VLIW) architectures.
"We're working on constructs for exploiting concurrency for processors, and we have some constructs in place for special-purpose function units," he said. "Where we're drawing a blank is how to efficiently describe bit-level parallelism. There are some big areas yet to be resolved."
Using the Intel IXP1200 network processor as a test case, the GSRC is seeking to develop a retargetable compiler infrastructure for a family of architectures. "Our goal is to have a compiler, assembler and instruction set simulator automatically be generated from a single processor description over a fairly broad class of VLIW architectures connected in a multiprocessing scheme," Keutzer said.
To that end, the GSRC is using the Trimaran compiler infrastructure developed by Hewlett-Packard Labs in collaboration with the University of Illinois. Researchers are also developing support for a broader range of VLIW architectures, dynamic run-time scheduling and multiprocessor configurations.
Asked how the outside world is reacting to his research, Keutzer replied, "Silicon vendors seem to think it's right on. But I would say the EDA industry in general just doesn't see this trend yet, even though these are the people whose lives will be changed the most by the trend to fully programmable circuits."
Designing new fabrics
Even if there is a move toward fully programmable platforms, somebody still has to design silicon. How to do that effectively in the gigatransistor era, where interconnect delays are a dominant factor, is the topic of the "constructive fabrics" theme headed by Larry Pileggi, professor of electrical and computer engineering at Carnegie Mellon University(Pittsburgh).
A "fabric," Pileggi explained, is a generic term for "circuit." An IP block, a complete system-on-chip or a new type of circuit design could be a fabric.
The idea behind constructive fabrics is on-the-fly assembly and synthesis of soft IP blocks, while trading off delay, power,
area and routability concerns.
The GSRC fabrics theme has ambitious goals. Over a 10-year horizon, it seeks to provide an ability to construct a 50,000-gate component with the same ease as a 50-gate macrocell today, and to let designers assemble 20,000 or more of these 50,000-gate components with the same level of automation they now enjoy in putting together a 50,000-gate standard cell block.
The emphasis is on soft IP, Pileggi said, because it's more portable to multiple foundries than hard IP. Pileggi readily admits that the challenge is to overcome the present performance advantage of hard IP.
Then there's the sheer task of assembling thousands of complex blocks. "We believe that a lot of the nasty low-level details will have to be abstracted away," Pileggi said. "Designers don't worry too much about individual cells today. When we reach gigascale, they won't think much about details inside a 50,000-gate block."
Just merging synthesis and layout is not enough, Pileggi said. "What we are really looking for is a complete predictive capability, where you have a very high-level representation of something, know how well you'll be able to construct it, and push a button. We're nowhere near that level of automation today."
Research projects under the constructive-fabrics theme run from high-level design to transistor-level details. One effort is looking at the problem of simultaneously partitioning and retiming large numbers of blocks. Another is looking at new approaches to synthesis using "don't care" wires. Yet another is examining repetitive patterns in IC layout, so as to make verification possible on a gigatransistor chip.
But new types of circuit fabrics are part of the research as well. A "wave-steered" fabric, for instance, promises predictability and performance as clocks steer signals through binary decision diagram (BDD) nodes. The concept of "noise-immune fabrics" suggests that signal and ground shielding is routed to every wire in the design. "This is a fairly extreme view," Pileggi said, "but looking at extreme views is part of this whole [GSRC] center."
Finding new metrics
The fourth GSRC theme, "calibrating achievable designs," is very different from the other three. "It's not as much focused on technical aspects, but more on the process of how we do CAD research, how we evaluate it and how we integrate that evaluation back into a feedback process," Newton said.
Project leader Andrew Kahng, associate professor of computer science at the University of California at Los Angeles, said the project attempts to answer three questions: What is the design problem going to look like in the future? How can we put together the right EDA solutions quickly? And did a given solution really improve the overall design process?
"The overall impact I see is that we would have much more directed and focused research," Kahng said. "We would not have grad students wasting their time reinventing the wheel. We would have better conduits among designers, EDA tool organizations and academic R&D."
The first aspect of the theme centers on the GTX (for GSRC technology extrapolation), a tool that provides a more formal way to develop a collaborative road map. It seeks to answer such questions as when inductance matters or whether 3-D extraction is required for timing convergence-questions that numerous companies and research groups are struggling to answer on their own, Kahng noted.
The GTX tool takes in parameter files and rules, and outputs various kinds of reports, plots and graphs. "It's really
a framework that allows you to capture your knowledge, manipulate that knowledge via rule chains and visualize
the implications," Kahng explained. "It's something that can be built by many people simultaneously."
The second aspect of the calibration theme is a relatively new idea: IP for CAD developers. "If you look at CAD you see some very fundamental building blocks, like placers, Steiner tree constructors and delay calculators," Kahng said. "The argument for reuse is very analogous to that for hardware systems it's a time-to-market and quality issue."
From that concept has arisen a multi-university Bookshelf project that collects and stores reusable EDA algorithms. It consists of 10 active "slots," or categories, which contain data formats, benchmarks, binary utilities, source code and documentation. Two of the slots are from Kahng's UCLA research on placement and hypergraph partitioning. The Bookshelf is envisioned as benefitting EDA vendors as well as academics. "The copyright policy is complete freedom of access and use for all purposes," said Kahng.
Finally, the calibration theme seeks to measure the impact of EDA tools through a "metrics transmitter." Kahng described the concept as "a little piece of a library" that's built into a tool, so as to produce human-readable output for such metrics as wire length and CPU time. It transmits data via the XML format over the Internet to an Oracle database. The metrics transmitter in UCLA's placer imposes less than 1 percent overhead on run time, Kahng said.
The four GSRC themes will be considerably refined in 2000, and four two-day workshops are planned to bring researchers together. But the nature of the project does not lend itself to specific deliverables and timetables.
"The intent is to give faculty a lot of control over their own destiny and to evaluate the program in terms of whether there are really interesting ideas coming out of the work," said Newton. In that, the GSRC seems to be succeeding.