SANTA CRUZ, Calif.An EDA startup with close ties to the University of California at Los Angeles (UCLA) is quietly preparing next-generation synthesis for large, high-performance PLDs. The startup, Aplus Design Technologies (ADT), came to light at the recent FPGA 2000 Conference in Monterey with the announcement of a partnership with Cypress Semiconductor Inc. (San Jose, Calif.)
ADT was founded in 1998 by Jason Cong, professor of computer science at UCLA and a well-known researcher in PLD synthesis and IC physical design. The company now has seven people, and is working on a project basis with FPGA and CPLD vendors, starting with Cypress. ADT's intent, however, is to eventually sell its tools to end users, either through silicon vendors or directly on its own.
While there are a number of PLD synthesis offerings today, they're not fully equipped for the coming generation of complex devices, Cong believes.
"Existing vendors are very capable at HDL compilation and generating netlists, but we really haven't seen an existing tool actively model the device and model the interconnect effect in the synthesis process," he said.
Cong noted that there's a lot of ongoing activity to couple ASIC synthesis more closely with layout, and he said the same kind of attention is needed for FPGAs and CPLDs. "The problem is just as bad on the PLD side, if not worse, because the interconnect has to go through programmable switches. It's thus more dominant," he said.
One of ADT's major thrusts is linking PLD synthesis more closely with layout. Another is architecture-specific optimization. Because HDL compilation works well today, the company will focus its initial efforts on optimizing netlists, Cong said.
Several PLD architectural changes are driving the need for new tools, according to Cong. One is the prevalence of hierarchy. No longer are FPGAs and CPLDs flat arrays of lookup tables, Cong noted. Another change is the increasing use of heterogenous programming elements. This calls for sophisticated resource tradeoffs, such as turning embedded memories into logic when memory is not needed.
"You have big variations in interconnect delays, and it's not possible for existing synthesis tools to handle them," Cong added. "They generate a netlist based on lookup tables, and hand it to the vendors to do place and route. There's a big disconnect there."
ADT promises to offer device-specific optimizations that more closely link logical and physical design. For example, Cong noted, an existing device might have both programmable interconnects and direct interconnects between lookup table elements. If the direct connections can be taken into consideration during synthesis, and used for the critical path, that can make a big difference in timing.
The company's goal, Cong said, is to "provide at least one speed grade or one process advantage" compared to existing design methodologies.
ADT's work with Cypress involves two aspects. The most immediate is the creation of a "flexible synthesis framework" that will allow Cypress to evaluate multiple heterogenous PLD architectures. "You cannot come up with a new architecture without thinking of how this thing will be synthesized and mapped," Cong noted.
A second goal is the creation of synthesis and optimization tools that will most likely be sold through Cypress. That's a ways out, however, since the partnership concerns new devices that Cypress intends to field in two years.
The ADT team includes key developers of UCLA's RASP system, an FPGA synthesis environment widely used in research. The company is not, however, taking software directly from RASP.
The startup's board of advisors includes Rajeev Madhavan, chief executive of Magma Design Automation; Giovanni De Micheli, professor at Stanford University; C.L. Liu, president of National Tsing Hua University in Taiwan; and Christopher Norris, vice-president of Cypress' PLD division.