SANTA CLARA, Calif. With the intent of making system-level models of virtual components (VCs) more available and usable, the Virtual Socket Interface Alliance (VSIA) has released a new documentation standard. The system-level interface (SLIF) standard provides for a complete description of VC communication at various levels of abstraction.
The spec, entitled "System-level interface behavioral documentation standard 1.0," is the first formal standard from VSIA's system-level design development working group (SLD DWG). The group had previously issued a reference document that defined terminology.
Chris Lennard, chairman of the SLD DWG, said that some providers of silicon intellectual property (IP) today provide system-level models, others don't, and the models that exist are not consistent. "Without the concept of an abstract model, it's very difficult to explore VC options that exist in your company or outside your company," he said. "We feel that although there are some models out there, they need to be tied to a physical implementation before designers can accept it."
The new spec, said Lennard, ensures that high-level descriptions of a VC can in fact be tied to a physical implementation. This is done by maintaining a hierarchical relationship between various levels of the interface abstraction.
Another goal of the spec is to get IP providers to document internal behavior separately from interface behavior. This is a key concept in system-level design, according to Lennard. "By applying this standard to VCs, we're making people document the function of a component with a mindset that's compatible with system-level design," he said.
Lennard said the SLIF standard will also help bring verification to a higher level. "This standard will allow you to hook your component into a transaction-based verification suite more easily," he said.
The standard's other stated goals are to reduce the time required for understanding VC behavior correctly; to help users build reusable VC models above the register-transfer level; to speed system integration by mapping abstract system communication into physical implementations; and to provide a way to verify a VC without revealing implementation details.
The new standard introduces the concept of "interface layering," or abstraction hierarchy. An interface layer is a translation wrapper that can take one level of interface abstraction to the next level.
For example, if the concept of a "blocking read" exists at the topmost abstraction layer, one layer of refinement below this might define the blocking read as a read action dependent on an asynchronous reset/acknowledge action. A deeper layer could bring in the notion of synchronous clocking actions in a final hardware implementation.
It's important to understand the conceptual reasoning for an interface action, and how the action is implemented in the final design. This requires a linkage of the interface layers, or abstractions, through a clear refinement mechanism.
The SLIF standard sets forth a core set of interface layer abstractions that must be delivered with a VC. It offers a method for specifying the interface layering principle adopted by the provider. It defines the structure for the description of each interface layer, and the definition of a behavioral syntax.
SLIF also provides a link between the interface and the VC implementations of models, and a technique for specifying the hierarchical relationships between interface abstractions.
Companies represented in the SLD DWG include ARM, Cadence, CoWare, Easics, Frontier Design, Hewlett-Packard, Ikos, Integrated Chipware, Mentor Graphics, National Semiconductor, Nortel, Philips Semiconductor, Ericsson, STMicroelectronics and Toshiba.
The 80-page SLIF document is available for download by VSIA members from the VSIA Web site. A nominal charge is levied for non-members.