LONDON Open-source licensing of 32-bit processor cores is gaining ground, as the European Space Agency recently made available its Leon-1 CPU core. Though the core has yet to be fully tested in hardware, its VHDL source code has been downloaded at least 150 times since Feb. 17 when the debugged core went up on the agency's Web site.
Some observers suggest that the free availability of Leon-1 and of another 32-bit architecture, OpenRISC 1000, could undermine commercial core licensors like ARM Ltd., MIPS Technologies and Sun Microsystems. Indeed, Leon's designer, Jiri Gaisler, said he's already been approached by "a very big mobile phone company" looking to cut processor costs. He would not name the company.
A spokeswoman for ARM Ltd., a leading licensor of processor cores, downplayed the impact of the free cores on her company's business.
OpenRISC 1000 was announced last week by an organization called OpenCores. It plans to make OpenRISC available free over the Internet but the source code is not yet available. The release date has been set back to some time in March. Leon-1, debugged in simulation, is now available online under a GNU Library General Public License (LGPL).
The Leon-1 core is described as a Sparc-compatible integer unit implemented as a configurable, synthesizable VHDL model. At 27k gates Leon-1 is expected to run at 100 MHz in an Alcatel Microelectronics 0.35-micron CMOS process technology. A post-layout simulation of the core in a Xilinx XCV300E-8 FPGA shows it occupying 5,300 lookup tables with additional block RAM and running at 45 MHz.
Gaisler, technical officer at the European Space Agency's Technology Center (Estec; Noordwijk, Netherlands), said the center plans to develop Leon as a flight-worthy core for European Space Agency (ESA) use by 2001, but others could use it for embedded applications before that.
ESA is a European-funded body equivalent to NASA. For most of its history ESA has standardized on the Sparc, originally developed by Sun Microsystems Inc. (Mountain View, Calif.). ESA now obtains Sparc processor chips for its satellite systems under an initiative it calls ERC32, from European sources like Temic, now part of Atmel Corp.
CPU control needed
"The problem with ERC32 is that it is a proprietary design, based on an original Cypress Semiconductor Sparc, so we can't really use it in system-on-chip designs," said Gaisler. "We need to have control of the CPU and for the volumes we require, a few hundred a year, we can't justify license fees and royalties," he said.
"The Sparc architecture is an IEEE standard so it is an open standard. There are no limitations on designing around it," said Gaisler. "However the trademark belongs to Sparc International Inc. We can't call Leon a Sparc but we can call it Sparc-compatible. I have been in touch with Sparc International regarding the licensing issues."
By offering Estec's implementation of the Sparc architecture under the LGPL scheme, Gaisler hopes to make the core acceptable to commercial organizations that could then add proprietary cores to produce system-chips.
"The library version of the GNU license means you only have to make modifications to the original core public upon request," Gaisler said. "You can take the core and put your own IP [intellectual property] around it and you don't have to make that IP public."
According to Estec, the Leon-1 processor is intended as a demonstrator that implements a minimum of interfaces and functions. Once Leon has been fully verified, a more complete processor, Leon-2, will be developed with such additions as a PCI interface, floating-point unit and DRAM controller.
Leon-1 includes a Sparc-compatible integer unit, separate instruction and data caches, a 32-bit memory bus with EDAC, PROM and SRAM support, an interrupt controller, two 24-bit timers, two UARTs, a 16-bit I/O port, write protection, power-down function and a watchdog timer.
Last October Dennis Rose, operations manager for the advanced software products group at Xilinx Inc. (San Jose, Calif.), downloaded an early version of the Leon and implemented it in the Xilinx EDA tool suite, but Rose said he did not run any code or test vectors on the simulation.
"We saw the core on a Thursday, downloaded it, synthesized it, ran it through the tool suite and got a successful result over the weekend that is, we got a bit stream that could go to an FPGA. We haven't actually programmed one.
"We originally got up to [simulated] 18-MHz clock frequency, but with some modifications to infer block-RAM in the Virtex it can run faster. But we haven't gone beyond that," said Rose.
"It's very portable and easy-to-use code. I am very enthused about what Jiri [Gaisler] has done," he added.
Gaisler said the center originally released Leon-1 last October but found some bugs. "Leon-1 Version 2.0 is debugged and running well in simulation," he said. "We'll be making the core as an ASIC this summer and we'll have real hardware on Xilinx in a week or two. The problem is we don't have any Xilinx hardware yet. We also have a team at Chalmers University [Gothenborg, Sweden] who are putting this into hardware."
Because of the compatibility of Leon-1 with Estec's ERC32 program, Gaisler has extensive software support on hand and available for downloading including a GNU C compiler and a cross-compiler for ADA-95, assemblers, linkers, debuggers and operating system support in the form of the RTEMS real-time kernel.
Other Sparc implementations are available for license under the Sun community-source licensing (SCSL) program but with a unit royalty due upon manufacturing. Sparc International Inc. (Santa Clara, Calif.) has been set up as an independent company to own and administer test suites that demonstrate Sparc compliance.
Fadi Azhari, group marketing manager for Sparc and SCSL at Sun Microsystems' microelectronics division, said, "The SCSL pertains to licensing of implementations of the Sparc architecture that we have done," indicating that other implementations could be done and, in theory, offered for free. "We've always taken a very holistic view to proliferate the architecture," he said
Azhari said that Sparc instruction set and architecture licensing and compliance testing were Sparc International issues.
Karen Anaya, chief executive officer of Sparc International, said, "The equivalent of the V8 [Sparc's version 8] is IEEE standard P1754 for a 32-bit open microprocessor architecture. But if the product has been run through V8 testing the only way to get that certified is to come through Sparc International. Otherwise they have to put a disclaimer in their documentation that it is not certified. They also have to acknowledge our trademarks."
The P prefix implies a draft and not-yet-ratified standard at the IEEE.
ARM's spokeswoman said the company does not see availability of free 32-bit processor cores as similar to its own business or competitive with it.
"ARM's business model is not just about cores," she said. "It's based on a full product road map and also on third-party support. That includes design companies, development tool support and operating systems support. It's not simple to build all the support that ARM now has in place."