SUNNYVALE, Calif. Simplex Solutions Inc. has tailored the new version of its VoltageStorm power grid and electromigration analysis system for system-on-chip (SoC) design.
David Overhauser, vice president and co-founder of Simplex, said that while the original VoltageStorm product tar-geted the full-custom and semicustom design market for analyzing large blocks at the transistor level, the new VoltageStorm SoC tool is a faster gate-level product that quickly analyzes entire SoC designs.
Power grid analysis tools have been too slow to run on entire SoC designs, Overhauser said, which forced designers to black-box memory and intellectual-property (IP) blocks and to only run analysis on the interaction of logic blocks.
"People thought that because most of these IP blocks had been preverified for power that they didn't need to be analyzed again. We are discovering with SoC [designs] you have to look at the entire design-not only the logic but the memories and IP as well-and see how the entire design's power grid is affected," said Overhauser.
The tool is 10 times faster than the transistor-level VoltageStorm product, thanks large-
ly to a new QIC analysis engine, Overhauser said. It also employs a power view library for creating power profiles of blocks used in an SoC.
"We are preprocessing cells and blocks and creating a power view library that allows VoltageStorm SoC to have the speed of a gate-level flow and accuracy of our transistor-level tool," he said.
The tool also boasts a mock-up view, allowing designers anywhere in the physical-design flow to define characteristics of particular blocks. "At the floor-planning stage of your design, for example, you can assign speeds to particular blocks and help in designing the power grid to see the best placement of those blocks in the overall design," said Overhauser.
The new tool lets designers apply the IR drop analysis from VoltageStorm before signal routing, so they can use the results during timing verification and avoid costly downstream engineering change orders to correct power-grid problems, he added.
In the VoltageStorm SoC flow, designers enter cell libraries and IP in GDSII and LEF formats into the tool, which automatically creates power view libraries. Designers use the libraries to create power mock-ups, then enter their mock-up and instance power consumption reports created by Sente's WattWatcher or Synopsys' Design Power into VoltageStorm SoC.
The product takes the DEF of a design and the models from the power view libraries and runs a power consumption and power grid analysis. The tool outputs graphical displays, plots and reports. "After analysis if a chip fails you can bring up the tool and use its interactive mode to do some experiments and what-if analysis, then generate a change report that can be fed back into the place-and-route flow," said Overhauser.
The tool can also run analysis over several layers of hierarchy. The company claims that beta customers have run five-metal-layer designs with 114,000 nets in 840 seconds. The automatic-view library setup took an additional 76 seconds.
VoltageStorm SoC starts at $150,000 for a perpetual license. It runs on Hewlett-Packard and Sun workstations.