LOS ANGELES Hardware design in the C/C++ language will play a key role at this week's Design Automation Conference (DAC), when Synopsys Inc. throws its considerable weight behind the concept with its first hardware synthesis tool based on the SystemC modeling platform. Frontier Design NV and CoWare Inc. will likewise announce SystemC compatibility for their own system-level EDA products, which are at least somewhat competitive with Synopsys' latest synthesis tool.
Despite that multivendor support, the SystemC class library isn't yet a universal standard, as other introductions make clear. CynApps Inc. (Santa Clara, Calif.) is announcing the latest release of its CynLib C++ class library proposal, and C Level Design Inc., which supports various class library approaches, will be at DAC with a cycle-accurate C compilation option .
Synopsys (Mountain View, Calif.) isn't the first EDA vendor to offer C language synthesis, but a SystemC announcement from the overwhelming market leader in ASIC synthesis is a milestone for the emerging market. Synopsys will announce the CoCentric SystemC Compiler, which essentially adds a C language front end to Synopsys' Behavioral Compiler.
Frontier Design (Leuven, Belgium) will announce SystemC compatibility for its A/RT Designer architectural synthesis tool. And CoWare Inc. (San Jose, Calif.) will add SystemC support to its N2C hardware/software codesign environment.
All three vendors must overcome heavy skepticism on the part of many chip designers about C/C++ hardware design. In a number of E-Mail Synopsys Users Group (ESNUG) postings, designers have variously called C language design unnecessary, cumbersome or inefficient, and some have noted that C language hardware design has been tried before with little success.
"I believe C/C++ exploration will have a niche but will not be the mainstream," consultant Cliff Cummings, president of Sunburst Design (Beaverton, Ore.), said in a discussion thread at EDTN's EEdesign.com Web site. Cummings, who organized a panel on system design languages to be held June 7 at DAC, said testbenches for C language models are not reusable for register-transfer-level (RTL) or gate-level design.
Many designers have a "natural reluctance" to move to a new language, noted Mark Flumenhoft, vice president of marketing for Synopsys' system-level design business unit. "But now, there's a new level of design complexity," he said. "More importantly, system-level folks are developing complex systems in C and C++, and we either provide a path that gets there smoothly or we go through a very time-consuming manual translation process."
That, he said, is where the new Synopsys product comes in. "SystemC Compiler allows the chip designer to take the C of the original concept and put it into a standard HDL flow," Flumenhoft said. "Until now, there's been a handoff gap."
SystemC Compiler has all of Behavioral Compiler's synthesis capabilities. It accepts SystemC code that conforms to Synopsys' synthesis coding guidelines. It outputs either a gate-level netlist or a synthesizable RTL description in VHDL or Verilog.
Not for everyone
Synopsys is not presenting SystemC as a solution to every problem a mistake it made with Behavioral Compiler. At the outset, the company is positioning the tool more at systems designers than RTL designers. The initial release accepts only behavioral SystemC code, with an RTL capability to come later.
The targeted applications are those served by Behavioral Compiler: primarily networking and graphics designs that lend themselves easily to a high level of abstraction, said Joachim Kunkel, vice president and general manager of Synopsys' system-level design business unit. But Behavioral Compiler needs coding in VHDL or Verilog, so it must be translated manually from the original C or C++, Kunkel said.
While the SystemC class library is an emerging standard, it covers everything needed to define hardware, said Kunkel. It lets users describe concurrency, signals, ports, components and component hierarchies.
Other providers will offer SystemC-based synthesis tools. But Synopsys, said Flumenhoft, is "leveraging SystemC Compiler on our entire synthesis excellence," using many elements of Design Compiler, including a common timing engine and DesignWare libraries.
Users still have to take existing C/C++ models and make them compliant with SystemC. "Usually you take existing C code and start adding things to it," said Kunkel. "It's not that much of a rewrite unless the original code is a total disaster."
Once that's done, they use the timing constraints that would be used for Behavioral Compiler. The synthesis capabilities are identical to Behavioral Compiler, including automatic and semiautomatic scheduling, resource allocation and a recently added graphical analysis feature. In the future, said Flumenhoft, SystemC Compiler will include some synthesis capabilities not in Behavioral Compiler.
Most users are expected to compile directly to a gate-level netlist. Synopsys expects the quality of results to be the same as for Behavioral Compiler, meaning area within 10 percent of handcrafted RTL code. SystemC Compiler can also output RTL VHDL or Verilog, which can be taken to an FPGA for rapid prototyping, though the output is not optimized for FPGA production design.
The output of two previously announced SystemC-based tools the CoCentric System Studio and CoCentric Fixed-Point Designer is not synthesizable by SystemC Compiler. To be synthesizable, SystemC code must still follow Synopsys coding guidelines, which are included with the tool's documentation.
For verification, users can co-simulate SystemC models using the SystemC kernel and an HDL simulator. Synopsys offers SystemC Simulation Interface packages for the Synopsys VCS and Model Technology ModelSim VHDL simulators, with others to be added later.
CoCentric SystemC compiler ships this week for Unix, starting at $40,000 per license.
While C language synthesis from Synopsys is a significant industry milestone, two of its allies in SystemC standardization CoWare and Frontier Design have offered forms of C language synthesis for some time.
This week, Frontier Design will announce that it has added SystemC version 1.0 compatibility to its A/RT Designer architectural synthesis EDA tool. As part of its design flow, A/RT Designer now accepts SystemC fixed-point designs, as well as ANSI C algorithms, and it can take either down to synthesizable Verilog or VHDL descriptions. Floating-point ANSI C code can be refined to fixed-point SystemC code either manually or automatically, using tools such as Synopsys' CoCentric Fixed-Point Designer.
"At DAC we, together with Synopsys, will show a SystemC design flow," said Herman Beke, Frontier's president and chief executive officer. "Now nobody needs to rewrite anything moving from C to HDL . . . Architectural optimization and exploration are there in A/RT Designer. And we have proven this with our own design services operation."
A/RT Designer with support for SystemC is in beta testing with select Frontier customers and is due to appear commercially in the fourth quarter. A/RT Designer seats purchased before the SystemC-enabled version was available will be upgraded free-of-charge. Prices for A/RT Designer start at $65,000 per seat.
Like Frontier, CoWare seems to be considering working with Synopsys on SystemC, but competing on tool features and performance. CoWare's N2C, however, is positioned as a codesign tool rather than a behavioral synthesis offering. CoWare is expected to demonstrate support for SystemC version1.1 in its N2C design environment at DAC. The full release of those capabilities is slated for N2C version 3.0 later this year.
Under the change, N2C will allow design entry in SystemC, import of intellectual property modeled in SystemC and output in SystemC, VHDL or Verilog. Hence, all of CoWare's hardware/software codesign environment including full-featured specification, analysis, partitioning, hardware/software cosimulation and debug, interface synthesis and HDL code generation is due to be accessible from SystemC.
"As a founding and leading member of the Open SystemC Initiative, we've brought to bear our extensive experience of C-based system-on-chip design," said Guido Arnout, CoWare's president and chief executive. "We're happy to use standard languages and compete on the added value of our tools and methodologies."
SystemC version 1.1 includes two capabilities CoWare has donated to the Open SystemC Initiative: the abstract communications protocols CoWare uses for interface descriptions and the remote procedure call capabilities that CoWare uses to handle certain system-level events.
SystemC 1.1, with CoWare's contributions, is available in beta form at the SystemC Web site.
Meanwhile, CynApps has announced that Cynlib 1.2, the latest version of its C++ class library proposal, is available for downloading. New features are claimed to make the library more compatible with EDA tools from third-party vendors.
New tool support comes from TransModeling Inc. (Cave Creek, Ariz.), whose SystemModeler design entry and verification environment will generate C++ code based on Cynlib. SystemModeler, a tool for generating C++ models and testbenches, lists for $20,000 on Windows NT and Unix platforms.