SAN JOSE, Calif. Another spin on combining ASICs and programmability has surfaced, this time from a startup with a logic cell that promises higher density and performance than an FPGA.
The technology being offered by eASIC Corp. (San Jose) ups the ante on LSI Logic Corp., which is developing FPGA cores to drop into its ASICs. The startup says its logic is more flexible than an FPGA and is better suited for building large pools of programmability.
Founded by former Chip Express chief executive officer Zvi Or-Bach, eASIC employs 25 engineers in two design centers in Romania, an unusual setup that was driven by Or-Bach's personal acquaintance with a programmer from that country. The company sports just a handful of employees in San Jose, and Or-Bach's own residence houses the company's U.S. headquarters.
Or-Bach's plan is to make eASIC a chipless company, selling its programmable technology, known as eASICore, through foundries as intellectual property. The idea behind eASICore is to provide programmability inside ASICs while avoiding some of the penalties of FPGAs, particularly in performance and density, Or-Bach said.
Using a 0.18-micron, six-metal-layer process, eASICore yields 30,000 gates/mm squared, about half the density of standard-cell ASICs but a considerable boost from the 1,500 gates/mm squared of FPGAs, Or-Bach said. Performance is enhanced as well: eASICore hits 400 MHz, he said, whereas FPGAs are only now breaking the 200-MHz barrier.
"The whole idea is that you are in line with standard cell performance and very close in density," Or-Bach said.
The idea of combining ASIC design with programmability is being pursued throughout the industry. With designs getting more complex and mask costs reaching $1 million for 0.15-micron parts, chip vendors hope to ease designers' workloads by offering some flexibility in the form of programmable logic.
One commonly cited use for that flexibility is in communications. Rather than wait for a completed standard and risk being late to market a designer could use programmable logic for functions related to the standard, cementing that part of the design only at the last minute, when the parts are ready to ship.
Programmability could also provide varieties of a particular chip. "You could get differentiated [versions] of your design," Or-Bach said.
LSI Logic next year intends to roll out its eFPGA program to drop programmable cores into its ASICs and thereby enable modest programmability. Actel Corp. is developing FPGA cores to pursue the same idea. And the major FPGA vendors are chasing the goal from the opposite direction, dropping ASIC cores into large FPGAs or attaching commonplace circuitry like a PCI controller to an FPGA bank.
The eASIC approach is not meant to supplant those other efforts, Or-Bach said, adding that there's no reason an FPGA core and an eASIC core couldn't coexist on an ASIC. But eASICores are better-suited to large blocks, he said, while LSI Logic's FPGA-core efforts are less ambitious. "When you read the [LSI] material, they clearly state you should limit yourself to 50,000 gates," Or-Bach said. "We are addressing the same type of need that LSI addresses [with its eFPGA cores]. But we are not ruling out that you might have a chip that has both."
Performance and density are enhanced by putting eASICore's programmability only on the top layer of metal, via the addition of "jumper" metal connections using the last one to three ASIC masks. Or-Bach said that makes the core more compact than an FPGA, where programmability occurs at the transistor level.
The idea was to replace "very structured [FPGA] connectivity" with a more flexible, rich connectivity, he said. The approach keeps the core from being dominated by interconnect, a problem that has plagued FPGAs as metal layers become more prolific. "The FPGA approach is starting to pay dearly as you add more layers," Or-Bach said.
In addition, eASICore's individual logic cells, called eCells, have a few features designed to improve performance. The cells use a pair of three-input lookup tables, compared with the four-input tables of standard FPGAs, allowing for simpler levels of logic. A multiplexer can combine the lookup tables logically to handle more complex tasks or to resemble a normal, four-input lookup table, if needed.
The lookup tables are fed by four inputs, two of them combined by a NAND gate. Those two inputs run at a higher speed to boost eCell performance.
Each eCell also has two inputs passing data through an inverter without performing logical functions. Those can be used for buffering or to amplify signals traveling a long distance. But they also let signals pass through eCells quickly if necessary.
The eASICore can be used in small, scattered areas or as large blocks, Or-Bach said. In the latter case, eASICores can act as dual-port memory to create large, programmable blocks of logic and memory.