Complex system-on-a-chip (SOC) designs are a major challenge. Companies are turning to platform-based design (PBD) techniques to develop SOCs with flexibility in mind to meet changing standards and market trends. Changes required for next-generation SOCs must be made quickly and efficiently to meet market window demands. By using PBD techniques, companies can rapidly develop many derivatives of a core SOC platform, customizing these core platforms by adding more hardware and/or software.
Traditional ASIC design makes it extremely difficult, if not impossible, to change out major hardware and software IP blocks because all of the interfaces to the IP blocks are hard coded into the design. If central parts of the design, such as the processor, bus or memory architecture, need to be changed, the entire design must be re-worked. If major blocks are added, new hardware and software interfaces must be added to the existing blocks.
Inter-twining an IP block's behavior with its interface in this manner means that, in order to offer a strong yet flexible IP portfolio, semiconductor vendors are forced to maintain a large IP repository including multiple variants of the same function for different buses. Add to this the fact that models of the IP blocks are too low-level and it's clear to see why the much-vaunted era of wide-scale IP re-use hasn't yet materialized.
What is platform-based design? It's the creation of a stable core-based architecture that can be rapidly extended and customized for a range of applications. Derivatives can be easily created by adding different software or hardware to the base platform. In this manner, a product family may be delivered instead of a single product, and future generations can leverage the hardware and software investments originally made. This, in turn, dramatically reduces the time to market, lowers development cost, and reduces chip costs.
PBD is a strong response from the semiconductor industry to provide internal product groups and system-house customers with silicon architectures and a range of IP, with enough flexibility to offer families of products for a given range of applications. PBD allows semiconductor companies to achieve this flexibility within the limits of their commercial infrastructure and IP portfolio, and on top of a stable enough basis, that meets the constraints of their manufacturing process and design methodology. It's effectively a balance between limiting IP choices to remain within the semiconductor company's commercial and manufacturing constraints, while offering enough flexibility to meet system-house customers' needs. Exactly where different semiconductor companies draw the line will determine how successful their PBD strategies will be. The winners will be those that enable greater customer flexibility.
In order to provide flexibility to the customer while meeting the constraints of time-to-market, there are some specific challenges to be met to implement a PBD strategy:
Verifying complex multi-processor designs with software
Only recently have platform-based design tools come to the market, and Coware has developed a tool that's been used in numerous platform-based designs by companies such as STMicroelectronics. Coware N2C enables the design team to explore multiple design approaches and examine different aspects of system behavior, then implement the system in software and hardware.
Interface Synthesis: The key to platform-based design
The key enabling technology for platform-based design is Interface Synthesis. Interface Synthesis helps designers rapidly turnaround platforms for the many different derivatives for a particular product line. Hardware components such as processors, CPU and/or DSP, buses, memories, and peripherals may be upgraded or changed. For the software, Interface Synthesis automatically generates the memory map for registers and the software drivers to communicate between the hardware and software.
Our design methodology lets designers separate the function from the communications. This makes swapping out one piece of IP for another much easier. It also allows designers to quickly evaluate the potential of one piece of IP versus another. The old way of design was so cumbersome that once a major IP block was designed in, it was rarely swapped out because of the required interface re-design.
Here's how Interface Synthesis works. After performing analysis at the untimed C level to determine an initial system partition, the designer selects a base platform from the available range. He then assigns functional blocks to either hardware or software and selects abstract communications protocols applicable for each block interface. Then N2C will synthesize the interfaces between the hardware and other hardware and software elements, elaborating the abstract protocols into the full detailed bus protocol for the selected processor and bus. Automating this tedious process frees the designer to focus on more value-added design. An additional benefit is that designers can easily examine new SOC design variants created by choosing a different hardware-software partition or IP model.
With Interface Synthesis, the interface between the IP block and the target processor or system bus can be designed without any detailed knowledge of the processor or bus specification, protocols, timing diagrams, memory map, and interrupt vectors. All of this knowledge is captured as part of the base platform.
Figure 2 - Sample Platform Description
Interface Synthesis: Critical new extensions for platform-based design
Now, Interface Synthesis has been extended to enable the creation of platforms before the full functional specification is known. Platform creators can now run Hardware-Hardware Interface Synthesis, which allows extensible platforms to be created with very limited knowledge of the functional specification. The platforms can consist of multiple processors, multiple buses, DMA, Interrupt Priority, and Encoders. These platforms can now be taken all the way to implementation before the executable specification for the product functionality is finalized.
A platform-based design methodology impacts both the platform creator and the platform user. The platform users require the ability to easily add software content and/or more proprietary hardware blocks to develop their unique product. Specific new functionality helps the platform user in two ways. First, another extension to Interface Synthesis means that Hardware-Software Interface Synthesis is now enabled for multiple processor platforms. Second, Interface Synthesis now generates a set of files that allows application software to be mapped onto the platform very easily. We will now look at these two new capabilities in detail.
Until now, multiple processor platforms were built by fully specifying one processor sub-system and fixing its interfaces, then adding the next. Only one processor is left enabled for Hardware-Software Interface Synthesis by the user. Now, a functional specification can be mapped to a multiple processor platform by performing Hardware-Software Interface Synthesis on each processor in turn.
For software developed within a conventional embedded software development flow, it hasn't been immediately apparent to the software developer how to map the embedded software onto the target processor in a Coware platform model. Now, as part of platform creation, a detailed Application Programming Interface (API) is automatically generated making it very easy to map embedded software to the target processors. This API consists of header files giving a comprehensive and clear link to the platform's memory map, and makefiles to help the software developer compile his program to the target processor correctly.
Figure 3 - A virtual platform allows software development before
the physical prototype is available
Providing a virtual platform
The benefit of a virtual prototype is the ability to debug both hardware and software prior to having access to the physical prototype. Traditional embedded software development and debugging begins with hardware development. The only bugs that may be identified are limited to ones related to the core processor, either the CPU or DSP. With a virtual prototype, not only are those bugs found and resolved, but the designer also can discover and resolve issues related to communications between the hardware and software, timing of this communication, and the servicing of interrupts.
N2C's new capabilities for PBD allow the benefits of virtual prototypes to be extended to providing virtual platforms. For PBD, it's more critical than ever to be able to provide a virtual system at the earliest possible stage. Furthermore, with the advent of multiple processor platforms, it's more critical than ever to provide a co-verification environment that is significantly faster than traditional HDL-based hardware-software co-verification.
The full system may now be tested at one time, and designers don't have to wait for the physical prototype to identify and resolve these issues. The cost associated with finding and correcting bugs on the actual hardware prototype is astronomical, and if these bugs aren't found early enough in the design cycle, the product may not even meet the market window.
The re-spins, when using a virtual platform, are at the front-end of the design process, and not at the end after the physical prototype is returned. The hardware teams have the ability to add hardware to the core platform, verify the hardware using the "real" application, update the hardware based on the results of running the real application, and continue this cycle with a high level of confidence of the product's completeness.
The same is true for the software teams. These re-spins are easily accomplished through Interface Synthesis for multiple cores and linking the software modules through the API.
The virtual platform enables the software and hardware teams to work in tandem throughout the design cycle rather than requiring that the software team wait until an actual hardware implementation is finished.
Platform-based design: Essential for fast-moving markets
The old way to design a SOC takes too long, makes a design that's too difficult to change, and often makes companies miss important deadlines. A platform-based design strategy will speed current and future designs.
Karl Van Rompaey is chief technical officer at CoWare, Inc. (Santa Clara, CA).