SAN JOSE, Calif. Cadence Design Systems Inc. will signal an aggressive approach to wrest some market share from Synopsys Inc. this week with its announcement of major improvements to its synthesis technology. The enhancements include data path synthesis, power optimization and design-for-test capabilities for the Ambit BuildGates and Envisia PKS products.
Of those, Cadence is most interested in making inroads with the high-end Envisia PKS, touting it as an alternative to Synopsys' Physical Compiler. Both are physical synthesis tools that incorporate synthesis with placement. Synopsys is well ahead in terms of announced tapeouts, but Cadence recently announced its second tapeout for Envisia PKS: a data decoder IC at Geocast Network Systems.
Much more is in the works, said Jeff Roane, vice president for synthesis, placement and routing marketing at Cadence. He said that Envisia PKS and Silicon Ensemble PKS have, between them, over 30 customers. About two-thirds are using Silicon Ensemble PKS, which incorporates synthesis technology into placement and routing, and one-third are using Envisia PKS physical synthesis, he said.
Synopsys, on the other hand, has over 30 tapeouts for Physical Compiler, said Thomas Ferry, vice president of marketing for physical synthesis at Synopsys. "Our observation is that many 'users' of PKS are actually Silicon Ensemble PKS users," he said. "In this mode, PKS appears to be more of a gate-level optimization tool than an RTL [register-transfer level]-to-placed gates physical synthesis tool."
In its third-quarter financial announcement earlier this month, Cadence announced a major deal with Texas Instruments that includes Envisia PKS and Silicon Ensemble PKS. Charlie Simon, manager of EDA software at TI, confirmed that his company's large mixed-signal group has adopted Envisia PKS as its primary physical synthesis solution but said it has not yet decided to replace any Synopsys tools.
At Geocast, Jim Jackson, vice president of hardware development, said Envisia PKS resulted in a timing correlation of 160 picoseconds between synthesis and final layout a difference of less than 3 percent. A detailed interview with Jackson is online at the EDTN EEdesign site.
Cadence has until now had difficulty in cracking Synopsys' near monopoly in synthesis, partially because Synopsys has a much broader offering. For example, Synopsys has tools for data path synthesis, power optimization and design-for-test (DFT). With version 4.0 of Ambit BuildGates and Envisia PKS, Cadence is claiming to match or exceed those capabilities.
Moreover, Cadence is claiming considerable performance advantages in the new release. Roane said that BuildGates 4.0 runs three times faster than the previous version, and that Envisia PKS, which is slower because it includes placement and global routing, runs 25 percent faster.
Building arithmetic structures such as data paths has not been a strong point for conventional synthesis tools, and for some time Synopsys has addressed that problem with a product called Module Compiler. Cadence is attempting to counter that with a tool called the Envisia Datapath Option.
Ketan Joshi, director of product marketing for synthesis at Cadence, said the new tool can automatically recognize data path structures in RTL code. It then separates them out and runs a data path synthesis engine in order to reduce area and improve timing. Among the capabilities are operator merging, in which related operators can be merged into a single component.
There's also an enhanced AmbitWare library for arithmetic operations, but Cadence doesn't use a static library, Joshi said. "Instead of picking from a prestructured library, this tool generates structures on the fly, based on design requirements." Components that can be easily inferred from RTL code aren't even in the library, he said. Those that can't, such as pipeline multipliers, are still generated on the fly in accordance with design requirements.
Joshi said that customers are seeing up to a 50 percent area reduction of data-path-rich designs and timing improvements averaging 17 percent. "And it all happens transparently, so that's a big advantage," he said.
Synopsys has also had a tool called Power Compiler for several years. Now Cadence is offering the Envisia Low Power option, which lets users specify power constraints. "You can not only describe constraints for power, but [also] the focus is on concurrent optimization for timing, area and power," Joshi said.
The new option looks at RTL code and finds areas where techniques such as clock gating might reduce power consumption. However, those changes aren't put into effect until the final result is confirmed at the gate level. Another key feature of the tool, Joshi said, is incremental power analysis. "The tool recognizes which power structures have changed and only calculates the power changes that are necessary," he said.
The DFT enhancements aren't part of a separate option, but are built right into BuildGates and Envisia PKS. For BuildGates, capabilities include RTL design-rule checking and scan chain insertion. Because Envisia PKS includes placement, it can go one step further and reorder scan chains. Automatic test pattern generation is still done with third-party tools.
Envisia PKS also includes clock-tree synthesis, a feature that was notably missing before. Now, said Joshi, there's no need to separately run Cadence's CT-gen clock-tree generation program.
Also new is the incorporation of the Pearl parasitic reduction and delay algorithms into BuildGates and Envisia PKS, which makes it possible to read parasitic files in several standard formats in order to improve the precision of post-route optimizations.
Ambit BuildGates and Envisia PKS 4.0 are available now starting at $12,000 and $100,000, respectively. The Datapath and Low Power options start at $30,000 and $24,000, respectively.