Vancouver, British Columbia - November 28, 2000 - Image Power, Inc. announced the immediate availability of a JBIG intellectual property (IP) core for the embedded semiconductor market. The first in a family of imaging IP cores, the JBIG IP core is designed for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) applications.
Image Power's JBIG IP Core was developed under contract with a communications infrastructure product company and marks Image Power's first licensing agreement to embed an imaging IP core into a programmable logic device. The JBIG IP core is capable of operating at 50 MHz when implemented in an Altera Flex 10K class FPGA device, the company said. The JBIG IP core is compliant with ISO IS 11544, implements a QM arithmetic coder, single progression sequential and supports FIFO based local bus widths of 8 or 16 bits.
"We are excited about being able to offer the first in a family of imaging IP cores which meet the specific needs of the programmable logic design community," said Stephen Swift, president of Image Power. "FPGAs offer hardware design engineers rapid time to market and ultra high speeds - critical in advanced imaging applications."
The JBIG IP core is available directly from Image Power, Inc. The license fee for the JBIG IP core is $20,000 per encoder or decoder or $36,000 for both per design instance in encrypted netlist form, plus a volume dependent royalty. Source code for the codec is available in the form of VHDL for $100,000. The company said it is currently developing JBIG2 and JPEG2000 IP cores.
Image Power, Inc.
Vancouver, British Columbia
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