HENDERSON, Nev. Aldec Inc., a longtime provider of FPGA design tools, will make its first foray into the ASIC market this week with Riviera, a Linux-based mixed-language simulator. Riviera simulates VHDL, Verilog and EDIF and comes with an HDL editor and source-level debugger.
The simulation engine underlying Riviera is from Active-HDL, Aldec's Windows NT-based simulator. But Riviera is not a Linux port of Active-HDL, said Aldec marketing vice president David Rinehart. "It's native Linux. It's the first step as we move toward a Unix-based verification suite."
Some of Aldec's FPGA customers are looking for more capacity and setting up server farms, Rinehart said, and Linux offers those users better performance than Windows NT. Aldec has found that Riviera runs up to five times faster in batch mode under Linux than under Windows NT on the same hardware platform, he said.
But the real aim of Riviera is to gain entry into the high-end ASIC design marketplace. "It's a natural progression for our company," said Rinehart. "We do have some ASIC customers today, but mostly they're using our tools for prototyping."
Riviera does not yet have ASIC vendor signoff support, however. Rinehart said Aldec hasn't been able to gain that in the past, because its products didn't run under Unix. Riviera is available first under Linux but is expected to support Unix in the first quarter of 2001.
Like Active-HDL, Riviera supports all current IEEE VHDL, Vital and Verilog standards. While EDIF simulation is primarily for FPGA users, Aldec has kept the function in Riviera. Both Active-HDL and Riviera also have a Tcl scripting interface.
But there are differences. Active-HDL is an integrated system that includes a text editor, a graphical entry tool, a block-diagram editor, a state-machine editor and a debugger. Riviera is modular, so designers can use other design entry or debugging tools or, conversely, use Riviera's HDL editor with other simulators.
Riviera does not include the graphical entry, state-machine and block-diagram tools offered in the Active-HDL suite, but those will be added later, Rinehart said.
As for speed, Riviera is equal to or faster than "the leading simulator for VHDL" but is two to four times slower than the "leading Verilog simulator," he said. Aldec was an early supporter of VHDL and has just recently added Verilog simulation.
A key selling point for Riviera will be its integration with the Hardware Embedded Simulation (HES) system that Aldec expects to sell early next year. HES promises to be an inexpensive, FPGA-based emulation system that allows users to progressively download portions of a design into hardware, thus supporting the concept of "incremental prototyping." HES is said to yield a tenfold increase in simulation performance on designs of more than 500,000 gates.
Riviera comes with a source-level debugging capability that lets users set breakpoints, see variables and view waveforms. Users can navigate between the HDL editor and the simulator. Alternatively, Riviera runs with third-party HDL debugging programs.
Riviera starts at $12,495, including the HDL editor and debugger. It runs on Red Hat Linux. Licenses will be transferable to Windows NT and Unix once those operating systems are supported.
The product can be downloaded from Aldec's Web site. Aldec also plans to offer Riviera on the pay-per-use e*ECAD site.