SAN JOSE, Calif. Synopsys Inc. made a serious play last week for FPGA business through an agreement with Xilinx Inc. to develop a design flow for system-on-chip FPGAs devices that combine hard silicon cores with arrays of programmable logic.
The yearlong partnership between Synopsys (Mountain View, Calif.) and Xilinx (San Jose) will help flesh out the viability of using C/C++ for system-level descriptions, a trend being tested in complex ASIC work.
Meanwhile, Altera Corp. (San Jose) has been working with similar concepts and is preparing its own design-flow announcement with Synopsys, said Bryan Hoyer, Altera's senior director of system-level products.
Both agreements will represent an investment for Synopsys in a traditionally scrawny FPGA market that could become important if programmable logic device (PLD) vendors' system-on-chip (SoC) efforts catch on.
The proposed Synopsys-Xilinx design flow would start with a C/C++ system-level description that would eventually be translated into an FPGA place and route tool. One goal is to allow designers flexibility when they consider which elements to implement in FPGA hardware and which to program as software into the hard-core CPU.
The CPU firmware and FPGA hardware normally are developed by separate teams using different tools. A design team working on an SoC FPGA first has to decide which elements to implement in CPU software or FPGA hardware, and then task each design team with its half of the project.
Proponents of the FPGA-based system chip want to simplify the process, providing a single language that contains a system-level description, coupled with tools that would handle the hardware/software split automatically.
That's the ultimate goal, but it's years away, by most estimates. The more immediate goal is to have tools that allow the designers to make that hardware-software partition arbitrarily, again using a high-level language for the initial system design.
In the absence of a perfect language, the best candidate to start from is C, because of the sheer number of programmers using it today, said Joachim Kunkel, vice president of system-level design at Synopsys.
"These system-level designers feel more confident working in C/C++ than in a hardware language like Verilog or VHDL," Kunkel said.
The C language combined with hardware description libraries such as those from Synopsys' SystemC initiative allows designers to verify algorithms more easily than in Verilog/VHDL, and it lets designers postpone the decision about which functions will be implemented in hardware and which in software, he said.
This is occurring despite the fact that no comfortable tool flow exists for C-based designs. The C code is first translated to Verilog/VHDL and then to register-transfer-level code.
The extra layer of translation required will probably lower the quality of the resulting circuit, so Synopsys' goal and that of Xilinx and Altera is to eliminate the middle step, translating C code into RTL files.
The agreement between Synopsys and Xilinx is targeted at developing a design flow that will allow systems-on-chip which Xilinx now calls platform FPGAs to be built from C/C++ system-level descriptions.
Some detail might be lost because of the abstraction of the C language. "It depends on the problem type," said Mark Flomenhoft, vice president of marketing for Synopsys' system-level design group. "For problems that are very much structured, where people understand the registers and the logic, they can refine it themselves before they do synthesis."
But generally, Synopsys expects the C-to-RTL design flow to yield the same circuits as a Verilog/VHDL-based flow, if not better, because both will hand off their RTL data to the same synthesis tools. "There is no difference in quality of results, because the synthesis is the same," Kunkel said.
In a move to support a project similar to Synopsys' SystemC initiative, Altera in June made a minority investment in C Level Design Inc. (San Jose, Calif.), which is developing a C library for hardware descriptions.
For now, Altera's SOPC (system-on-programmable-chip) Builder tool allows designers to alter the division line between hardware and firmware.
"Over time, we sell the technology in an iterative nature instead of reaching out to the far star," Hoyer said. "We have some tools which allow the engineer to do hardware-software partitioning, looking forward to the day when the tool will do that."
Such tools are still far from becoming a reality, Hoyer warned, but he was optimistic that they will emerge in time.
"Remember, it was only a few years ago in PLDs that people said, 'You've got to use schematic design, because synthesis would not work,' " Hoyer said. "Over time, the technology gets good enough."
Gary Smith, EDA analyst with Gartner Group Dataquest (San Jose, Calif.), said that the idea of a C-based design flow for SoC FPGAs is solid but that there's more work ahead if these chips are to become truly reconfigurable platforms.
"This is going to work, and I think it's an important tool. But the whole concept of reconfigurable computing" is difficult, Smith said.
"If you mess with your reconfigurability in an ASIC, you risk screwing up your verification," Smith added. "And nobody is [really] talking about verification."
Synopsys' revenues have come mostly from ASICs, with FPGAs being a less lucrative area. In part, this is because programmable logic vendors compete based on their hardware: Tools are given away so that users become familiar with them and are reluctant to try competitors' offerings.
"Unfortunately [FPGA software] is cheap, because Xilinx and Altera keep subsidizing it," Smith said. "I think they're hoping as is Exemplar, inside Mentor Graphics that someday Xilinx and Altera will wake up to the fact that they have to support a strong, healthy EDA vendor in their marketplace."
But Kunkel said Synopsys' embracing of the SoC FPGA doesn't mean it's resigned to selling more seats of cheaper tools. Rather, he sees the possibility for the SoC FPGA to beget higher-priced tools.
"I don't expect this trend to continue for a long time, that FPGA tools have to be cheap," Kunkel said. "We cannot develop software at those prices to solve the complexity of the designs these people want to do."
The SoC FPGA design flow is separate from Nimble, a Synopsys research project targeted at reconfigurable architectures. Nimble specifically finds points in a system where parallelization could be used and that therefore would lend themselves to implementation in hardware.
Synopsys officials continue to stress that Nimble remains in the lab and is not necessarily destined to become a product. Company officials declined to state how much of a contribution, if any, Nimble is expected to make to the Xilinx project.