LONDON Tenison Technology EDA Ltd. has enhanced its flagship Verilog-to-C compiler, VTOC, by adding output support for the SystemC variant of C++ as well as multiple compilation output modes.
Tenison (Cambridge, England), a startup formed in January 2000, was until recently a one-man company of founder David Greaves, a University of Cambridge lecturer who serves as chief technology officer and acting chief executive for Tenison. The company's primary asset is Greaves' VTOC, which allows hardware designers to take cores written in the Verilog hardware description language and translate an individual core or assembly of cores into C to speed up simulation. Tenison has expanded its staff to five and now has five customers for VTOC, which is available for Solaris, Linux and Windows (Win32) operating systems.
Greaves claims that VTOC generates a cycle-accurate implementation of a complete Verilog design in a C-language program that can then be compiled and that typically runs 50 to 100 times faster than a conventional behavioral simulation.
While Verilog licenses are usually hard to come by within a design group, a C-language version of the design can be executed on any processor without license. According to Greaves, the result runs about 100 times faster than Cadence's Verilog-XL and ten times faster than Verilog-NC. Tenison first offered VTOC earlier this year at $2,000 for an annual license per company site, irrespective of the number of seats.
Tenison said it expects to expand its customer base in 2001 and to hold its first private placement and venture capital funding round.
VTOC version 15 offers the latest enhancements and is available for free download and evaluation from www.tenisontech.com. It includes SystemC-compatible output modes and a native C++ multiple compilation mode. A demo system and an evaluation license together with examples are also available from the Tenison Web site. Current VTOC licensees can get a free upgrade to version 15 of the software.
SystemC is a community source set of libraries and EDA tools from the Open SystemC Initiative intended to facilitate the high-level modeling of systems in object-oriented C++ and intellectual property exchange.
"We're working to SystemC version 1.0 and version 1.1 for testing against. They are the only ones available for download at the moment," said Greaves.
"We're not heavily involved in SystemC. It's really only an output mode for VTOC for those people who do want to be involved in SystemC," Greaves said. "In terms of the changes to VTOC, it was a painless procedure, although there's a big learning curve associated with SystemC."
In addition to supporting SystemC, VTOC's C++ native mode allows sections of Verilog to be compiled into C++ at different times and then combined with other modules using the system link editor.
There is a large performance benefit to using the native multiple compilation approach compared with using the SystemC netlist mechanism to link together separately compiled sections, according to Tenison.
To support the VTOC compiler Tenison has developed a set of libraries and header files called Tenos. "Tenos is an umbrella term for the files you need to compile the Verilog to get an executable program," Greaves said.
Both the SystemC and the Tenos approach to multimodule support are organized so only modules being changed need to be recompiled. This speeds up recompilation and allows larger designs to be handled. In either system, a suitable size for an individual compilation is 1,000 to 50,000 lines of Verilog code, or about 5,000 to 50,000 gate equivalents.
VTOC version 15 is still available at $2,000 per site per year, regardless of the number of seats, although Greaves said this would likely increase significantly and change to a per-seat model in 2001, as the company moved to establish its commercial footing.