SAN JOSE, Calif. Crafting the first language-to-silicon flow for the new Superlog design language, Get2Chip.com Inc. this week will release Superlog support for its Volare architectural synthesis tool.
The commercial synthesis support strengthens Superlog's bid to become the next-generation design language. But Superlog has a way to go to match the broad vendor support already amassed by the SystemC proposal, backed by Synopsys and CoWare.
Toward that end, Superlog creator Co-Design Automation Inc. is slated to launch an online Superuser forum of customers and EDA vendors Monday (Jan. 22) that will help shape the future of the language. The move is a step toward the eventual standardization of Superlog, which remains proprietary despite Co-Design's stated goal of an open language.
Superlog is a Verilog superset that includes constructs from the C programming language. Because of its Verilog compatibility, it has earned good reviews from chip designers in such forums as the E-Mail Synopsys User's Group, where some designers have expressed considerable skepticism about C language hardware design.
The addition of Superlog input to Volare "is a very important announcement for Superlog," said Gary Smith, chief EDA analyst at Gartner Group Dataquest. "The language has been gaining support in the design community."
At the same time, Smith said, the Synopsys-backed Open SystemC effort has become the target of increased scrutiny. "Once it was realized that SystemC 1.0 was in fact a higher-level RTL [register-transfer level] language, not really an ESL [electronic system language], there have been some fairly intense discussions on where this thing is going," Smith said. "The safe bet [on the next-generation design language] is still SystemC, but the doubt concerning C/C++ is growing."
To be sure, SystemC has considerably more momentum. Pete Hardee, director of product marketing for CoWare Inc., noted that the Open SystemC Initiative has a 13-member steering group and around 5,500 users from dozens of companies, and that over 20 EDA products now support SystemC. The competing CynLib C++ class library from CynApps Inc. has also drawn some vendor support.
In Hardee's view, Superlog is more a complement to SystemC than a true competitor: "My sense is that Superlog is quite strong with Verilog designers who are looking for C-like extensions for testbench design, but there is no adoption at the system level or in the software community. He acknowledged that SystemC 1.0 focused on RTL design but added that the current, 1.1 beta version adds system-level enhancements.
Superlog has won endorsements from 12 EDA vendors, mostly small companies or startups. Aside from Co-Design Automation's own Systemsim simulator and a graphical entry tool from Expressive Systems Inc., Volare is the first commercial EDA tool to support Superlog, said Dave Kelf, Co-Design's vice president of marketing. Five or six other EDA vendors are actively working on Superlog support, Kelf said.
Co-Design has announced one Superlog tape-out: a DSP chip containing an intellectual-property (IP) block from Freehand Communications AB, one of the user participants in the new Superuser forum. Superlog customers Nortel, Ericsson and Micronas are also participating in that forum. SystemC has no announced silicon tape-outs.
Get2Chip and Co-Design have worked closely together to hone Superlog for synthesis efficiency, said Bernd Braune, president and chief executive officer of Get2Chip (San Jose, Calif.), which has no plans at present to support SystemC. "Users tell us Superlog is a better language," Braune said. "It's closer to Verilog, and there's an easier transition from Verilog. I haven't talked to a customer who wants SystemC yet."
Get2Chip has the unenviable task of competing with Synopsys Inc., which controls the vast majority of the synthesis market today. But Get2Chip executives said the company is confident that Volare offers a unique combination of architectural, RTL and "topology-driven" synthesis, with better timing information than existing behavioral synthesis flows.
Thus far, Volare has supported behavioral or RTL Verilog input. The tool produces gate-level netlists with placement directives. With the Superlog support, users can go directly from Superlog to gates.
Braune said Superlog would allow Verilog users to "move up one level of abstraction" and take advantage of some helpful new constructs. Those include dynamic processes, which enable modeling of loop pipelining, and sequential assertions for protocol checking and virtual interfaces.
Tiny Get2Chip is hoping Superlog will put it on the map and propel it to the same kind of success that Synopsys had with Verilog in the late '80s. "We want to repeat history," Braune said.
Co-Design, for its part, is convinced that "RTL as we know it today will not be the entry medium of the future," said Simon Davidmann, president and chief executive officer of that company. "It will be Superlog, Systemsim and Volare."
But Superlog is still evolving, and there's no publicly available language reference manual (LRM). At present, Braune said, Get2Chip is working closely with Co-Design to sell Superlog synthesis to a limited set of customers. Co-Design has granted Get2Chip a free, nonexclusive license to use Superlog.
"The details of all the sales agreements have not been fleshed out completely," Braune said. "Right now, it's more important to offer a technical solution to people and have some people successfully produce silicon." Braune said he was holding off on naming customers in the absence of silicon tape-outs.
Braune expects full customer availability sometime in the second quarter for Superlog synthesis. Get2Chip will continue to expand its architectural Superlog support as the language evolves, he said.
The purpose of Co-Design's Superuser forum is to speed that evolution. The e-mail-based forum will be moderated by Co-Design chief technology officer Peter Flake. Davidmann said the forum includes about 75 active participants, including customers, 12 EDA vendor partners and some university groups.
"This is not a support line; it's a language forum rather than a product forum," said Davidmann.
"The Superuser forum will communicate online and share experiences and ideas about how to refine the language, how to use it and how to do architectural design," said Braune.
To build further momentum behind Superlog, Co-Design has scheduled a seminar to demonstrate the use of the Superlog language, Volare synthesis and Systemsim simulation. The seminar, "Breaking the RTL Barrier," is scheduled for Jan. 30 in Santa Clara, Calif., alongside the DesignCon 2001 conference.
"At the seminar we will be showing more of the language than ever before," Davidmann said, indicating that a series of presentations planned for 2001 is part of Co-Design's strategy for bringing the language into the public domain.
At present users have to sign a nondisclosure agreement (NDA) to receive detailed information about Superlog. But the company is moving toward both openness and standardization for the language, said Co-Design's Kelf. Standardization may not occur until 2002, but the company intends to "open" the language earlier, in stages, as it's formalized, he said.
"We'll open up the necessary pieces so Get2Chip users can use it straight away," he said. "They won't have to sign an NDA with us."
Superlog received a good review from Nick Skelton, vice president of hardware engineering at Freehand Communication. "The use of Systemsim simplified and sped up the verification task," he said. "If Systemsim was not available, the length of the verification cycle could have caused a significant issue for our overall time-to-market for the DSP core. Our first customer completed a successful tape-out in December 2000, with silicon samples expected early 2001."
Get2Chip claims Volare is the first implementation tool to support a system-level design methodology, where full-chip, architectural synthesis and timing analysis are performed on blocks that may be described at the behavioral, register-transfer and/or gate levels. The tool runs on the Sun Solaris and Linux operating systems and includes a Java front end.