SANTA CLARA, Calif. New details about the emerging Superlog design language came to light at a seminar at the DesignCon 2001 conference this past week. Co-Design Automation Inc., the creator of Superlog, teamed with Get2Chip.com Inc. to run a public demonstration of Superlog synthesis on a frame buffer design.
Superlog is a superset of Verilog that supports C language constructs and system-level design modeling features. While the language is proprietary, Co-Design Automation has stated that it intends Superlog to become a public-domain standard, and is gradually revealing details about the language at industry seminars. Get2Chip announced in January that its Volare synthesis tool will support Superlog.
Dave Rich, applications director at Co-Design Automation, told attendees at the DesignCon seminar here that Superlog represents an "evolutionary" approach to design. "If you know Verilog and you know C, you already know a little bit of Superlog," he said. "You can slowly add constructs as you get familiar with them."
Rich noted that Superlog contains the entire Verilog 2000 language specification. In addition to C language constructs, it adds constructs for protocol checks, coverage checks, assertions, temporal procedures, processes, queues, and other system-level modeling and verification capabilities.
Rich said that Superlog "cleans up" Verilog and adds some VHDL-like features, such as user-defined types and enumerated types. "All the features you like in VHDL are in Superlog," he said.
Side-by-side comparisons of C language code and Superlog code show relatively little difference. Superlog code uses a "$display" construct in place of the C language "printf." But what really distinguishes Superlog are the special features it contains for hardware and system-level design.
Superlog, for example, has a "process" statement that simplifies algorithmic pipelining. Processes can dynamically create or destroy pipelines. Designers can also use queues or reentrant tasks to make code more precise.
Superlog also has the ability to place pins, or bits, into interfaces. "An interface is a collection of signals, but it's more than that," said Rich. "You can have tasks in interfaces. It's an object-oriented approach. Now you can have a signal such that everyone connected has an interface available to them."
Protocol checking is a Superlog verification feature that makes it possible to test behavior by specifying the properties that designs should have. Assertions promise fast, efficient checks that can be run with simulation.
Rich also provided a closer look at Co-Design Automation's SystemSim, a Superlog simulator. SystemSim, Rich claimed, is the first simulator to support the relatively new Verilog 2000 specification. And with its CBlend interface, SystemSim lets users link in C code without going through the Verilog Programming Language Interface (PLI), Rich said.
"You can call C from Verilog as if it was the same language, and the reverse is also true. You can write a C program and call Verilog tasks and functions," said Rich. "You don't need pipes and sockets to manage two simulation environments."
The Verilog PLI, Rich said, was developed years ago by Phil Moorby one of the creators of Superlog as a "hack to keep people away from the internal database of Verilog." Going through the PLI, Rich said, carries a "tremendous performance overhead."
In the frame buffer demonstration, Rich noted that Superlog eliminates many of the pragmas, or compiler directives, needed for VHDL or Verilog code.
An overview of Volare's architectural synthesis was provided by Taher Abbasi, director of design and applications at Get2Chip.com. He showed how Superlog can be used to exploit such Volare features as algorithm pipelining, chaining, memory inferencing, resource sharing, and register sharing. Volare works with Verilog as well as Superlog, but Superlog makes it easier to work at a higher level of abstraction, Abbasi said.
Co-Design Automation plans to reveal further Superlog details at a seminar on the first day of the HDLCon 2001 conference, Rich said. HDLCon 2001 will take place Feb. 28 to Mar. 2 in Santa Clara, Calif.