Much as good jazz is all about the synergy between different musical points of view, physical design is all about the synergy between point tools and the range of data that emerges from those tools. And just as with its musical counterpart, physical design is at its best when all of the tools involved yield up a design solution that is both elegant and optimized.
Music buffs will argue that jazz is fairly easy to recognize, but pretty tough to define. Similarly, the industry today debates whether "physical synthesis" is a point tool category unto itself within physical design, or is actually something a bit more elusive. Currently, the term physical synthesis seems to be vaguely defined by some vendors as a process that performs some placement functions in conjunction with RTL synthesis.
Gary Smith, chief EDA analyst for Dataquest says, "It's getting pretty difficult to separate these tools [into a specific category of physical synthesis]. That's why I'm calling the tool set IC implementation. They can be sold as point tools, but lose most of their effectiveness. They only exist as point tools because the vendors - in this case, Synopsys [offering Physical Compiler] - haven't completed their IC implementation tool set. You'll notice that Cadence stopped talking about PKS [Cadence's Physical Knowledgeable Synthesis], a point tool, as soon as they introduced Integration Ensemble."
Kurt Keutzer, former CTO of Synopsys and current professor of E.E.C.S. at U.C. Berkeley said, "Physical design is the process of taking a netlist of components, each of which has a physical description, and translating that into a physical implementation that obeys process design rules. The key steps are still placement of the objects and routing among them."
He explains that the recent changes in design tools were precipitated by the move from the previous paradigm where distinctions were clearly drawn between front-end and back-end design. "Unfortunately, synthesis had a great model, but bad data. P&R had great data, but a bad model." Keutzer adds,"Synthesis isn't very incremental. Thus, you would iterate and then have a brand new netlist for place and route and have to start from there again [repeating the process]." So, a top-down approach began to present major concerns to the designers because of its tendency toward inaccurate initial capacitance calculations, an inability to handle top-down timing constraints, and annoyingly inaccurate internal timing models, Keutzer said.
The new physical design tools, according to Kuetzer, are providing improvements on several fronts. They offer better capacitance analysis in advance of synthesis, yield better timing in placement, and the tools are more effective than the previous generation of offerings because they provide better buffer insertions to account for longer wires.
Bigger may be better
Cadence Design Systems, Inc. (San Jose, CA) is, clearly, one of the major players in the physical design space - having historically owned a huge market share at the back-end of the design flow. Jeff Roane, vice president of marketing for synthesis and place and route, says that physical synthesis uses P&R technology to more accurately estimate timing. He explains that Integration Ensemble, introduced in Febraury 2001, is a hierarchical RTL-to-GDSII design implementation environment.
Another established tool vendor in physical design - Avanti Corp. (Fremont, CA) - hasn't been idle of late either, bringing out new technology to meet the .13-micron push and the increasing complexity of system-on-a-chip (SOC) design. "We believe that we need a new product every three to five years," said Michael Jackson, head of western engineering at Avanti.
The company brought out a stable of new products in January 2001 that improved on their current place-and-route tool set. Astro is a P&R system that is built on top of Avanti's Milkyway database and is geared toward ultra deep submicron (UDSM) design and includes a detailed router that concurrently optimizes timing, power, and signal integrity. Jackson says, "In Astro, we can also invoke clock-tree synthesis technology that's embedded as part of the placement process."
Released along with Astro was Columbia, a top-level router, and Cosmos, a full custom design tool. Asked if there would be any major vendor changes in the physical design space in the immediate future, Jackson replied: "There are too many [tool vendors] in the place-and-route space for the long haul."
Referring to a December 2000 tapeout survey conducted by ESNUG's John Cooley, Dataquest's Smith says, "Unfortunately designs tape-out, but tools don't. A tape-out produces a final GDSII file. That's [a process] done by IC layout tools." What EDA vendors are trying to say [in the ESNUG survey] is that their tool has been used to produce actual silicon. That, of course, has caused [some] confusion. The [Synopsys] Physical Compiler tape-outs could also be counted as Avanti tape-outs. [Therefore], the best way to read Cooley's survey was that the engineer listed the tool he/she thought was the most critical tool in the flow."
Cadence's Roane says that, in the past, the physical designer would come in and do a trial place and route beore synthesis. He argues, that isn't necessary now. The designer can create a constraint file with physical constraints, which helps the process to move more quickly for the logic guy. On the flip side, he says, a back-end designer has to come up to speed on timing constraints.
Moving to smaller process geometries requires developments in equal measure on two fronts: advances in physics and improvements to the design tools to meet the challenges of the new technologies. Whereas the center of the bell curve of manufacturing output today is hovering at .18 micron, the curve is relentlessly and steadily moving toward .13 micron.
Dataquest's Smith also says, "Trust me. It'll be hard enough getting to .13 micron. These things are done in specific steps as laid out by the SRC [Semiconductor Research Corporation] Roadmap. Each process jump determines everything from how we build the actual fab building, to the silicon wafer, to the processing equipment, to the chemicals used, to the semiconductor packaging, to the types of EDA tools needed." He added "EDA tools and some of the other technology such as packaging are good for [the lifetime] of two process technologies. The .25 micron to .18 micron [geometries] needed last generation's EDA tools, but .13 micron to .10 micron will need this next generation of tools. There are process shrinks, which really don't [generate] much further innovation - .15 micron is [just] a shrink of .18 micron."
Robert Smith, vice president of marketing and business development for Magma Design Automation, Inc. (Cupertino, CA), says the process generation migration is prompting a big transition in the tool market.
And, to add to the complexity, in a big design flow with different groups of engineers working on different pieces of the project, a common database with all logical and physical data is crucial. He agrees that Cadence is now doing in their new tools what Avanti has traditionally done - provide a common database, but different data models for different parts of the flow. Meanwhile, according to Smith, Magma has chosen to use a common data model instead of a common database. It remains for the users to determine if common database or common data model strategies will prevail.
Managing the mergers
The increasing need for physical design tools is having an impact on the business landscape as well.
Recent mergers between Sente, Frequency, and Sapphire Design Automation have resulted in an expanded Sequence Design (Santa Clara, CA), a company that provides an amalgamation of the three former companies' core expertise in power, timing, and signal integrity, respectively. Eric Filseth, vice president of corporate marketing and strategic alliances, sees a big opportunity for the company as a "complementary" tool vendor in the physical design space.
According to Filseth, "Physical synthesis doesn't go far enough below .18 micron. It doesn't tell you about the coupling between wires. Also, the optimization at the end of physical synthesis is missing."
"Controlling timing in big chips is all about driving capacitances, which is especially a big problem below .5 micron," Filseth says. "We don't agree with redrawing the wires - as is the case with most tools - after routing.
Instead, we choose to drive the wires in a different way until the design is satisfactorily optimized."
Monterey Design Systems (Sunnyvale, CA) is one of a small cadre of companies that have attempted to challenge the established physical design players in the last three years. In March 2001, Monterey merged with design planning company Aristo Technology (Cupertino, CA). The Monterey moniker will be the name of the new company and Monterey president and CEO Jacques Benkoski sees the merger as a natural partnership between Aristo's front-end technology and Monterey's back-end tool set.
"If you want to automate the back end of the flow, physical design planning is necessary earlier." The core of Monterey's physical design set is Dolphin which uses "global design technology" to perform concurrent optimization of such design areas as placement, routing, timing, and logic, among others. Additionally, contrary to the published results of the ESNUG count, Monterey has been active in the tape-out arena. In March 2001, an Infineon Technologies design taped-out with the company's Dolphin tool on .18-m process technology.
Adding to the roster
Plato Design Systems, Inc. (San Jose, CA) seems to fit the role of newcomer in the physical design space, releasing their first tool, Nanoroute, in April 2001. The router, described as a "dynamic router" by Joe Xi, vice president of marketing for the company, might challenge the current physical design methodology that uses a chip- and top-level router.
"We see a big bottleneck in the routers at .13 m, at 10 to 20 million gates." The standard grid-based routers have limited capacity to deal with an unlimited complexity, which makes the current tools unreasonably slow when routing, according to Xi. "We call our tool a dynamic router because it combines the flexibility of a gridless tool with the speed of a grid-based router."
Celestry Design Technologies, Inc. (San Jose, CA) - the result of the March 2001 merger between BTA Technology and Ultima Interconnect Technology - produces tools that do physical analysis at the cell level, including signal integrity analysis and extraction. Dale Pollek, vice president of marketing, notes that their expertise in signal integrity is developed out of a sense of focus and, additionally, questions the notion of any one company realistically owning the flow. "Our tool performs silicon-accurate timing signoff and, between place and route, there's a clock synthesis tool," Pollek said. " If IC design were becoming a commodity or old hat technology, then it's conceivable for one [company] to own the flow. But the reality check part is that ICs are getting more complex and so are process-related issues. "
Just as jazz is at the root of much of American culture and music, so the physical design portion of the industry can be viewed as the foundation upon which EDA was built. Bob Smith of Magma says: "There's a major discontinuity every 10 to 12 years in EDA." The increasing rush to produce and perfect tools for physical design is the discontinuity happening in EDA today. Free jazz or bebop, the vendors of this new generation of tools will need, however, to answer to the beat of the users if they want to ensure that they land this gig.
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