SAN JOSE, Calif. Parasitic on-chip inductance is looming as a new challenge as high-end ASICs push toward 0.13 micron and approach frequencies in the gigahertz range. But as IC companies begin to tackle the problem, the tools and methodologies for resolving it are in their infancy.
Digital ASIC designers have thus far paid scant attention to inductive effects, but times are changing. Inductance no longer presents a problem for IC packages, microprocessors and RF devices only. On digital ASICs, inductance is beginning to affect power, clock and bus structures.
"Inductance is the next problem," said Gary Smith, chief EDA analyst at Gartner Dataquest. "The shift to 0.13 micron seems to be the reason. Anything over 600 MHz is RF, and you can't deal with RF without knowing about inductance."
For most signal lines, resistance dampens inductive effects. But when frequencies are high, and lines are wide and long, self-inductance can wreak havoc with delays and mutual inductance can cause noise, crosstalk and other signal-integrity problems. On ASICs, inductive effects are generally confined to power and clock lines, although long, on-chip buses can cause problems as well. The low resistance of copper interconnect may also present inductance problems.
All 0.13-micron digital designs above 500 MHz will experience inductive effects and not just for power and clock grids, said Vic Kulkarni, chief operating officer at Sequence Design Inc. One example provided by Sequence examines a 10-mm copper bus structure drawn 5 microns wide with 2-micron spacing in 0.25-micron technology. With 1-GHz frequency and a 50-picosecond rise time, Sequence calculates that self-inductive effects will impact delay by as much as 32 percent.
But ASIC designers may not need to worry about inductance outside of power and clock nets, said Lou Scheffer, fellow at Cadence Design Systems Inc. "Signal nets are all done at minimum width," Scheffer said. "And if you make a long line work by using buffers or repeaters, you keep things to the point where inductance isn't one of your big problems."
One place where inductance is a problem today is Sun Microsystems Inc. The company is running into inductance problems with processor designs, but not yet with ASIC designs, said Sunil Joshi, vice president of design automation at Sun's computer resources processor products group.
"As you go into deep submicron, you get a lot more inductive coupling as lines get closer," Joshi said. "The difficulty of on-chip inductance comes from the fact that the return paths for the current aren't easy to figure out. You may have a wire that influences another wire that is not even close to it."
Joshi said that Sun is trying to figure out a methodology for determining when inductance might be a problem, deciding what to extract and simplifying the data into something manageable. Clock lines are the greatest concern, he said, although inductance may also affect some signal lines. "It's hard to say what tools we need. I don't know if there's a methodology that exists," Joshi said.
The difficulty of inductance modeling and extraction is underlined in two "Inductance 101" papers given at the 2001 Design Automation Conference (DAC) last June. The papers note that on-chip inductance results from three concurrent effects. Currents flow through conductors, creating magnetic fields. As they vary with time, the magnetic fields induce electrical fields. These electrical fields, in turn, act on other conductors, causing voltage drops.
The classic problem with inductance modeling is that inductance always involves loops, but the return paths cannot be predicted in advance. In fact, the return paths may change with frequency on a cycle-by-cycle basis. Inductance modelers thus use a "partial-inductance" approach, generally employing what are called Partial Element Equivalent Circuit (PEEC) models. Partial inductance defines each segment as having its own return loop with infinity.
The PEEC models, however, create another problem extremely dense RLC (resistance/inductance/capacitance) matrices that can choke Spice simulators. An alternative approach involves less accurate models that include resistance and inductance, while leaving out capacitance.
The DAC papers discuss design practices for minimizing inductance, including shielding, dedicated ground planes, net ordering, interdigitated wires and staggered inverter patterns. A separate DAC paper submitted by Synopsys Inc. researchers argues that the best way to control inductive cross-coupling is by using interdigitated power lines to perform differential signaling.
The "L" in RLC extraction isn't good enough because mutual inductance, denoted in Spice by the "K" element, is also essential. In general, self-inductance causes delay degradation, while mutual inductance causes noise and crosstalk problems, said Haris Basit, vice president of business development at OEA International.
But mutual inductance can actually lower the inductive effect. In one example presented by OEA, an RC extraction on a clock network yielded a skew of 18 ps, which jumped to 48 ps when self-inductance was calculated. But the figure changed back to 29 ps with mutual inductance.
"When you have a lot of 'K' elements, all the Spice simulators we know of become extraordinarily slow," said Basit. "They're pretty good at RLC, but if you look at a clock network, there may be tens or hundreds of thousands of mutual inductance terms."
OEA's Cheetah is a 3-D field solver that uses partial inductance models. It's employed in the company's Net-An product, which is said to be able to extract inductance and mutual inductance for several hundred nets in a few hours. "The question is, can you simulate it. We're not the limitation, it's the Spice simulator," said Basit.
But most other observers say the real problem is with inductance extractors both in terms of the return-path assumptions they must make, and the massive amounts of data they produce. "The obvious gap right now is in extraction," said Jim McCanny, technical marketing director at Cadence. "There are a number of circuit simulators that can deal with inductance. But when you get to large digital circuits, the problem becomes much more difficult to analyze."
From the outset, EDA startup Nassda Corp. has portrayed HSIM, a fast Spice-like simulator, as a product that can simulate inductance without a significant slowdown. That's because HSIM is not event-driven, said Simon Young, product line manager at Nassda. He said HSIM might run anywhere from 5 percent faster to 50 percent slower while simulating inductance, with mutual inductance tending toward the upper end of that range.
But HSIM customers simulating inductance are doing their own extraction by hand, Young said. "Extraction tools are not mature. There are some great difficulties. Return-path determination is more of an art than a science," he said.
Sequence's Columbus-RF is a 3-D interconnect extraction tool that uses the PEEC approach to model loop inductance. It thus examines self-inductance with a return-path current, but models don't include mutual inductance. Users can specify a return reference net, or the tool can use the substrate as a default. Columbus-RF claims to be within 20 percent of such field solvers as the FastHenry from the Massachusetts Institute of Technology and Raphael from Avanti Corp.
A new version of Columbus-RF adds an "automated return-path detection" algorithm that looks for closely spaced traces. Sequence also recently announced that its ShowTime static-timing analyzer can use inductance information from Columbus-RF to calculate delays.
Right now, the Sequence inductance solution is aimed at critical nets. "ShowTime is ready to use full-chip extracted values, but the [inductance] extraction is not there yet," said Sequence's Kulkarni.
Avanti's Star-RCXT extracts self-inductance, and the company plans to address mutual inductance later on, said Bari Biswas, product manager for Star-RCXT. He said Avanti uses a "modified PEEC" model approach that takes multiple return paths into account. Accuracy varies widely, he said, ranging from 1 to 15 percent of Raphael.
Star-RCXT claims to offer a full-chip inductance solution. One key is speeding simulation by extracting capacitance separately from inductance and resistance. "It is definitely less accurate, but this is one of the things one would do to handle full-chip inductance extraction and simulation," Biswas said.
Cadence, meanwhile, is preparing what it claims to be a full-chip, 3-D, RLCK extraction capability for its Assura RCX product. It uses a "return-limited" inductance approach that's outlined in an ICCAD 2000 paper given by researchers from Cadence and Columbia University. The company claims this approach runs much faster than PEEC models, while coming close in accuracy.
Terry Ma, senior product marketing manager for Assura RCX, said the new capability is at beta sites now and is expected to be released in the first quarter of 2002. He also noted that Cadmos, acquired by Cadence earlier this year, has some technology that can reduce RLC matrices in Spice simulation.
Synopsys' RailMill product can extract inductance in power grids, and the company is hard at work at a broader inductance-modeling capability, said Raul Camposano, Synopsys chief technical officer. In addition to extraction, he said Synopsys will add inductive cross-coupling to its PrimeTime timing analyzer. There is little demand for such a capability today, Camposano said, but he predicted that inductance will "definitely" become a problem for the next generation of ASIC designers.
References for on-chip inductance
Design Automation Conference 2001
Inductance 101: Modeling and Extraction. This tutorial paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as skin and proximity effect.
Inductance 101: Analysis and Design Issues. This paper gives a tutorial overview of the analysis and design issues related to on-chip inductance effects.
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. This paper argues that crosstalk in high-speed technologies is best controlled by re-deploying inter-digitated power lines to perform differential signaling.
Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. In this paper, researchers from Cadence Design Systems and Columbia University discuss the "return limited" inductance approach behind a full-chip RLCK modeler.
"Net-An," a Full Three-Dimensional Parasitic Interconnect Distributed RLC Extractor for Large Full-Chip Applications. One of the first papers to discuss parasitic on-chip inductance effects, from the perspective of OEA International's Net-An product.
Sequence white paper
Is Inductance Becoming Critical for Deep-Submicron Interconnect? This white paper describes how and why inductance can become a problem for deep-submicron designs.