SAN MATEO, Calif. Synplicity Inc. has put a performance-enhancing algorithm into the latest version of its Amplify Physical Optimizer software and added retiming for Altera Corp. FPGAs plus a new timing-analysis engine to the latest version of its Synplify Pro FPGA synthesis tool.
Version 3.0 of the Amplify tool includes the Total Optimization Physical Synthesis (Tops) advanced placement algorithm, said Andy Haines, vice president of marketing for Synplicity, based in Sunnyvale, Calif.
The Tops technology, which does simultaneous placement and optimization, essentially boosts synthesis results, giving up to 50 percent timing improvement over the previous version of Amplify, said Haines.
The tool synthesizes and performs detailed placement of the critical paths to ensure optimal timing. Later, Amplify synthesizes the remaining portions of the design and guides a given FPGA vendor's router to implement the rest.
Synplicity has also added BlockRAM support to the Amplify tool. It enables the software to view and assign logic to BlockRAMs, Haines said.
The latest version of Amplify now performs automatic design-rule checks (DRC) to ensure BlockRAM capacity is not exceeded before moving on to place and route. "The DRC checks to see if there is room for a BlockRAM in a specific region," said Haines. "If a user tries to assign a BlockRAM in an area where there is no room, DRC will flag the error so it does not occur in place and route."
Amplify also includes floating-region support for Altera Apex devices, an automated pin-assignment user interface and new device support for Altera's Apex II and Mercury devices and Xilinx Inc.'s Virtex II FPGAs.
Also, the advanced timing engine originally developed for the Synplify ASIC tool is now part of the Synplify Pro FPGA synthesis tool, Haines said.
"In ASIC synthesis you need to have a very fast, interactive timing engine so that as you are doing the synthesis process, you can check timing to see if you are meeting or not meeting constraints," he said. "The kinds of constraints in ASIC have been more complex than in FPGAs because the timing models for ASICs are different." Hence the ASIC timing engine was added "so FPGA users can have more control over synthesis."
Version 7 of Synplify Pro also is equipped with an automatic re-timing feature for users of Altera devices. Previously, designers had to manually analyze critical paths and move registers to balance delay. Haines said the automatic retiming repositions registers within combinatorial logic to balance routing and thus improve circuit performance.
Synplify Pro also boasts a tighter link with Altera's Quartus II design software. Synplify Pro 7.0 starts at $19,000. The Amplify Physical Optimizer, available as an option to Synplify Pro, begins at $25,000. Customers already on maintenance will get the upgrades at no cost.