The most significant development of the new year in electronic design automation may be the advent of integrated, "IC implementation" tool suites that incorporate both logical and physical design. But these tool suites won't just focus on the traditional goal of timing closure they'll have to consider signal-integrity and power issues as well.
IC implementation, a new marketplace recently defined by Dataquest, encompasses single tool suites that take register-transfer-level (RTL) descriptions from synthesis all the way through placement and routing. A recent Dataquest report predicted this market will grow from $29.4 million in 2000 to $494.9 million in 2005. A controversial ranking gives Synopsys Inc. 64 percent market share in 2000, followed by Magma Design Automation Inc. at 24 percent, Cadence Design Systems Inc. at 10 percent and Monterey Design Systems Inc. at 2 percent.
Less controversial is the notion that front-end and back-end electronic design automation (EDA) flows are merging into a single flow. Observers say that synthesis, placement and routing must all become one process to prevent endless iterations. And at 0.13 micron and below, controlling signal integrity and optimizing power become just as important as meeting timing goals.
At 0.13-micron geometries, "parasitic effects are so interrelated that concurrent analysis is necessary both in the synthesis and placement-and-routing phase of the design, said Gary Smith, the chief EDA analyst at Gartner Dataquest. "This is beyond the capability of point tools."
As a result, Smith said, the IC implementation tool set is one of the top three priorities in EDA today. "As far as the competitive environment is concerned, it's No. 1 for the next 18 months," he said.
Semiconductor industry experts apparently agree. The latest release of the International Technology Roadmap for Semiconductors, issued in 2001, calls for integrated tool sets that perform concurrent analysis and optimization of many factors, including power, signal integrity and process variability.
At the beginning of 2002, complete IC implementation tool sets are still in their infancy. Cadence claims a complete RTL-to-GDSII flow with its Silicon Ensemble-PKS (SE-PKS) tool suite, but has yet to ship Integration Ensemble (IE), which is expected to be its primary offering in this area. Magma's Blast Chip offers RTL synthesis through placement and routing, but most Magma customers are still using Synopsys synthesis.
Synopsys' Physical Compiler takes users from synthesis through placement, but Synopsys' routing strategy is uncertain in the wake of its pending acquisition of Avanti Corp. (see Dec. 10, page 1). Meanwhile, Avanti has complete placement and routing, but is not actively selling RTL synthesis. Monterey also lacks RTL synthesis.
As they assemble their tool sets, all of these vendors realize that the current mantra of "timing closure" will have to change. Jacques Benkoski, president and CEO of Monterey, thinks a new term is needed.
"We are clearly moving from a timing-closure flow to a design closure flow," Benkoski said. "Today we have to deal with IR drop, power routing and noise issues. As we move to 0.1 micron there will be even more effects. You cannot optimize timing without looking at all these effects simultaneously, or you're back to an iterative flow."
The other burning issue, Benkoski believes, is hierarchy. "If you don't deal with hierarchy you won't be able to deal with complexity," he said. "We're talking about hierarchical management, not just bottom-up partitioning in a flat implementation flow."
When it comes to predicting signal-integrity and power problems, as well as managing hierarchy, silicon "virtual prototyping" is the way to go, according to Charlie Huang, vice president of marketing and business development at Cadence. In 2002, he said, Cadence will bring silicon virtual prototyping acquired from Silicon Perspective Corp. into SE-PKS and IE, along with signal-integrity analysis technology it acquired with the purchased CadMos Design Technology Inc. That combination, he said, will allow "correct-by-construction" design of complex ICs.
IR drop has become a serious concern, Huang said, because at 0.13 micron and below, IR drop can induce timing shifts or "grayouts" of portions of chips. To combat IR drop, engineers need to lay out power grids correctly. To help, Huang said, Cadence will roll out power-planning capabilities for SE-PKS and IE this year. These capabilities will let designers optimize power rails before placement and routing is complete.
Huang said that the move to copper interconnect is providing some relief from electromigration concerns, but has resulted in a need for tools to be "copper friendly." He also said that Cadence this year will offer an inductance analysis and extraction capability. "Inductance hurts power grids and power supplies, and can cause multiple components on a chip to couple," he said.
Synopsys will focus heavily on signal integrity this year, said Tom Ferry, vice president of marketing for physical synthesis at Synopsys. He identified four signal-integrity issues that customers are most concerned with crosstalk's effect on timing, crosstalk's effect on functionality, IR drop and electromigration (EM) on power and signal nets.
In 2001 Synopsys rolled out PrimeTime-SI, which lets designers look at the effect of crosstalk on timing. But there's more to be done, Ferry said. "Over the next six to nine months, you'll start to see the effects of crosstalk on functionality being handled," he said. "You'll see initial solutions for IR drop and EM. This is something we'll be working on for a couple of years."
What will be most significant, Ferry said, is the integration of these analysis capabilities into a comprehensive solution. "As opposed to having a point tool for EM, you'll have to analyze it throughout the flow," he said.
Synopsys is also known to be working on an upgrade to its Chip Architect design planner, code-named Hidden Dragon, that will extend the company's hierarchy management capabilities. Ferry promised an "advanced solution" that makes it possible to look at multiple levels of the design simultaneously.
Avanti's focus in 2002 will be the deployment of Astro, which is just now starting to be used in production flows. One difference between Astro and Apollo Avanti's previous placement and routing solution is that Astro offers more concurrent signal-integrity analysis, said Noel Strader, Avanti's director of corporate technology marketing.
"You have to concurrently optimize not only timing but also your clock tree, signal integrity, rail analysis and logic, and do all these concurrently as you're doing the physical implementation," Strader said. These capabilities required separate analysis tools with Apollo, but not with Astro, he said. Strader also noted that Avanti is preparing a "significantly faster" circuit simulator, called Star-HSpice XT, that can be used to analyze crosstalk and power rails.
Magma cannot comment on what will be coming up in 2002 because the newly public company is still in the middle of a quiet period, said Bob Smith, vice president of product marketing at the company.
However, he spoke of the need for additional work in power analysis. "When you start at the back of an envelope, you need a general power estimation capability," he said. "Then you want to use that information intelligently when you lay out the chip."
Monterey added crosstalk analysis capabilities to its Dolphin 2.0 release last month. But the main thing that's going to be new in 2002, Benkoski said, is that integrated tool sets will be used for production designs.
"At the moment, if you were to look at designs done in a truly integrated way, you could probably count with not much more than the fingers on your hands," Benkoski said. "This year's focus will be a change of methodology to an ability to do designs in a more integrated way."
The recently released latest ITRS-2001 road map, at http://public.itrs.net/, gives an interesting perspective as to the challenges faced by designers as they attempt to keep to the demands of the latest IC process advancements.
The following online references can be found at company sites:
"Static Crosstalk Analysis" (a Synopsys technology backgrounder)
"Crosstalk Aware Static Timing Analysis Environment" (ST Microelectronics Synopsys Users Group 2001 paper)
"Signal and Design Integrity" (Cadence Design Systems white paper)
"Noise-Aware Timing Analysis" (Cadence Design Systems white paper)
"Impact Of Coupling On Interconnect Delays: Devil Is In The Modeling" (Sequence Design white paper)
"Designing Noise-free in Deep Submicron" (Sequence Design white paper)
"An Innovative Approach to Managing Signal Integrity" (Magma Design Automation whitepaper)
"Signal Integrity Issues and Solutions" (Monterey Design Systems white paper)
"Inductance 101: Modeling and Extraction" (Design Automation Conference 2001 paper)
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