As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This article looks at one of the key design-for-test (DFT)technologies that will help lower the cost of test by reducing test time, as well as test data volume.
This technology, called reconfigurable scan architecture, is used to apply test patterns to the device in many different ways. The technology has matured with time to fit in the design flow, and is generally accepted by the IC design community. This article describes the application of reconfigurable scan chains in two different scenarios.
The need for DFT
The quality of an IC is a function of the yield and the testing performed to reject the defective product. Thus, IC testing is an important part of the manufacturing process of the IC. Testing is performed on automatic test equipment (ATE) using test patterns (stimulus and responses) that are dependent on how the design was implemented.
Figure 1 shows a flow where the design is modified to make it easier to test. In this example, DFT technology and tools such as automatic test pattern generation (ATPG) and fault simulation are used to create the test patterns that will be applied by the tester.
Figure 1 -- IC design flow with DFT
Since the cost of testing an IC has increased dramatically, overall testing has come under close scrutiny. As a result, every test activity that is spread across the flow must evolve to be more cost effective. An underlying trade-off is being made between silicon overhead and test cost impacted by test application time and test data volume. Some common DFT techniques use the addition of test points to an existing deign. This will reduce the number of test patterns that are created by the ATPG tools, thus reducing the test data volume. There are other techniques that can be used within the widely adopted scan DFT methodology in order to reduce not only the test application time, but also the test data volume.
Scan reconfiguration technology is one technology that can help reduce the overall cost of test, as measured by the test data volume and the test application time.
With the widespread adoption of scan DFT in digital ICs, the type of test patterns that are used for testing have become predictable and uniform. This uniformity of the test patterns is being leveraged by the ATE industry to develop testers targeted for devices that use DFT. Numerous configurations of testers are being created for different application-specific needs in order to reduce the cost of testers. This is very different from the older testers, which are fixed in configuration, but can handle multiple applications.
In a similar manner, DFT logic in the design can be configured to adapt to any tester configuration to maximize the utilization of the available testers. A typical test floor would have testers with different capabilities and sizes available to test different types of ICs.
Figure 2 -- IC testers have different configurations
Figure 2 provides a pictorial representation of a typical test scenario when the test floor is populated with testers with different capabilities. In this example, an IC with 32 scan chains will be tested. The test patterns require that 64 pins on the ATE have scan test capabilities -- 32 for scan-in, and 32 for scan-out. If the test floor has the four testers as shown, the IC could only be tested on the tester with 64 or more pins. This would leave out the smaller tester configurations from being used. Furthermore, the tester with 256 scan pins remains unused, and the scan resources are underutilized, resulting in longer test times.
The test application time is dominated by the time it takes to scan-in or scan-out the scan chains, as it is a serial operation. Since a design has a fixed number of flip-flops that are to be distributed across the scan chains that shift in parallel, fewer scan chains would result in longer scan chains and hence longer test application time. Thus, reduction in test application time requires an increase in the number of scan chains for the design.
The ideal scan configuration for the 16 scan pin tester is 8 scan chains, 32 scan chains for the 64 scan pin testers, and 128 scan chains for the 256 scan pin testers. Therefore, in a heterogeneous tester environment, reconfigurable scan technology can be used to better match the DFT configuration in the design to the tester configuration for optimum utilization of testers and reduced test application time.
While reconfigurable scan technology consists of the DFT portion of the solution, other changes need to be made to the patterns that allow for the test pattern data to be applicable to all the configurations without replicating the test data several times. What's needed are retargetable test patterns, which basically allow for the test patterns and the associated DFT technology to better match the design to the tester. Retargetable test patterns would have test data with selectable protocols to use different scan configurations.
Reconfigurable scan chains
Having detailed the need for a reconfigurable scan technology, it is appropriate to now describe what reconfigurable scan chains mean.
Scan chains are created from functional flip-flops that are configured into a shift register when some scan-enable signals are set to the appropriate value. The resulting scan chain is a serial connection from a scan-input through flip-flops to a scan-output. As a result of this structure, the internal flip-flops are controllable to any logic value and any internal state in the flip-flips can be observed.
This makes the flip-flops operate like inputs and outputs of the design, for all practical purposes. Figure 3 shows a design with 32 scan chains. In a typical design, multiple scan chains are created to shift in parallel, so as to reduce the total time it takes to shift values into and out of the flip-flops. A scan chain configuration is static for a given configuration of the design.
Figure 3 -- Flip-flops converted into multiple scan chains
A design may have multiple configurations to provide different functionality. For example, a design may provide access to the scan chains as a single scan chain for board level access to the chip through a IEEE 1149.1 Tap Controller interface. The same design may be tested during wafer sort through multiple scan chain configurations. Hence, different configurations of the design may require different set of scan chains. These needs are integrated into a single structure by the addition of multiplexers.
Figure 4 shows how multiple scan chains in the design are configured using multiplexers to allow all the flip-flops to be part of a single scan chain, or part of multiple scan chains depending on the value set on the select signal of the multiplexers.
Figure 4 -- Multiplexers in scan chains allow multiple configurations
This reconfiguration technology, which was used across different methodologies, is being leveraged for retargetable test patterns to better match the DFT and associated test patterns to the tester. Thus, many different scan-configurations have been created for the same test patterns, making it possible to test the design under different modes to better match the tester needs.
Scan reconfiguration improves test patterns
Scan chains can also be reconfigured to adapt to the scan test patterns generated by the ATPG tool. In general, testing for manufacturing defects (also called faults) in a device requires very few input/outputs, and scan values, to be fully specified. The rest of the values on the pins can be don't cares (Xs). The approach is to recognize the existence of a large number of X's and reconfigure the scan chain to reduce both test data volume as well as test application time. Tests in the internal representation of an ATPG tool look like the following.
Since scan chains are rigid structures, the ATPG tool would typically fill the X's with random logic values before fault simulation. Test patterns are hence fully specified tests. In reality most of the logic values need not be fully specified, and they can remain as X's. The sparse test data can be easily encoded or minimized.
A method called dynamic scan chains leverages scan reconfiguration technology to bypass segments of the scan chains that have X's in the test patterns. Figure 5 shows a reconfigurable scan chain that allows for all flip-flops to be available in a single scan chain, or in smaller segments. As shown, the scan segments need not be disjointed for dynamic scan. Each one of the tests can be modified, based on the X's, to be applied to a smaller scan segment, thus reducing the test time as well as the test data volume. The user can tradeoff against test time and the silicon overhead in terms of the number of scan chains and the associated control.
Figure 5 -- Scan reconfiguration allows scan chain reuse by test data
Lowering the cost of test spans the entire domain from design to the ATE world. DFT techniques implemented at the design stage impact the overall cost of test. Test time and test data volume are significant factors that affect the overall cost of IC test. By augmenting the widely adopted scan DFT methodology with reconfigurability, both test time as well as test data volume can be considerably reduced.
R. Chandramouli is a Product Line Manager for Test Automation Products in Synopsys. He has more than 15 years of experience in multiple disciplines of test across many companies, including Sun, Intel, Mentor Graphics, and LogicVision. He is a senior member of IEEE and chairman of the test development working group in the VSIA. Contact him at firstname.lastname@example.org.
Rohit Kapur is a principal engineer at Synopsys. His research interests are in VLSI test. He is chair of the IEEE 1450.6 committee, which is creating a test language for cores. Contact him at email@example.com.