FREMONT, Calif. Promising unprecedented speed and capacity, Avanti Corp. this week is unveiling Orion_ec, a formal equivalency checker that replaces the company's Design Verifyer offering. Avanti is making the announcement shortly before its expected acquisition by Synopsys Inc., which has a directly competing product, Formality.
Lee LaFrance, the head of formal verification products at Avanti, said Orion_ec was designed by the same team that developed Design Verifyer for Chrysalis, before that company was purchased by Avanti. Orion_ec, however, is "completely new from the ground up," LaFrance said.
Orion_ec is, on average, three times faster than Design Verifyer, and uses one-third the memory footprint, LaFrance said. This advantage may rise to a factor of ten for multimillion gate designs, assuming Design Verifyer could run the comparison, he said. "We wanted to make it the best tool out there so it would win every benchmark," he said.
But LaFrance acknowledged that the tool faces an uncertain future in light of Avanti's pending acquisition by Synopsys.
"Obviously this is something we started a few years back, before the Synopsys merger was anywhere in view," he said. "Until the merger is complete, we've been told by the government to continue competing. We feel that once the merger is complete, Synopsys may see this as something really good to have in their portfolio of tools."
The new tool reflects a learning process, LaFrance said. "We opened up the equivalency checking market with Design Verifyer in 1993," he said. "Along the way we learned a lot about how to do formal methods better, and how to do compilers better. We learned a lot about circuit models as well."
LaFrance said that Orion_ec ran an 8.5 million-gate customer design in just 1.8 Gbytes of memory in two hours. Its "nearest competitor" took 7.6 Gbytes of memory and 12 hours, he said. LaFrance wouldn't name the competing tool, but it's likely to be either Synopsys' Formality or Verplex Systems' Conformal product.
The key innovation in Orion_ec appears to be its improved compilation technology. The compiler with Design Verifyer required everything to be resident in memory at once, LaFrance said. That's not the case with Orion_ec, which allows the compiler to process larger circuits and store information in smaller memory footprints.
Also new is a "self-regulating verification controller" that can switch between the various comparison engines in Orion_ec. "It's important to have a central control mechanism, and what Design Verifyer had wasn't so centralized," he said.
Finally, a new "verification portal" provides a user interface redesigned for ease-of-use. Designs are easier to set up and debug, with an enhanced ability to trace problems back to source code, LaFrance said.
The first available version of Orion_ec will offer gate-to-gate comparisons only, and will work on flat 20-million-gate designs within a 4-Gybte memory footprint. It will be available June 1. While the Synopsys merger date is currently unknown, it appears likely Avanti will still be a separate company at that date.
The RTL-to-gate version of Orion_ec, slated for availability late in 2002, comes with more uncertainty. "We do have a merger in the middle there, and all plans after the merger will have to be re-evaluated," LaFrance said. Avanti does not reveal pricing for new products.