The proliferation of electromagnetic compatibility (EMC) directives during the 1990s became the latest in a long series of issues to upset the balance between logical and physical PCB design. As designer education and software tools began to catch up with requirements, EMC became simply another constraint issue for the hardworking design engineer. Ensuring your product has sufficient immunity to electromagnetic interference (EMI), and does not interfere with other equipment, is simply good design practice.
What has changed, however, is that increasing system complexity and performance has increased the likelihood of signal integrity (SI) problems. Simultaneously, time-to-market pressures have reduced the time available to verify and modify designs. Lengthy design iterations are no longer an option for most companies - and as board complexity increases, become an even less viable alternative. General engineering "rules of thumb" applied at the design and layout stages have, in the past, kept most designers out of trouble; however, techniques such as using lower frequency components and avoiding those with fast edge rates may be neither appropriate nor sufficient for today's designs.
The key to meeting your signal integrity requirements while meeting costs and deadlines is to anticipate problems at the earliest possible stage of the design. Rather than designing the product with one set of tools, then checking for problems with another, EMI and other signal integrity requirements should be constrained at the very beginning of the design, and a true rules-based design flow employed. The signal integrity tools must be fully integrated with the board design tools to ensure an uninterrupted design flow -- a fundamental change from previous methods where signal integrity checking was essentially an add-on process.
The latest generations of high-speed prototyping tools give the engineer the ability to constrain for parameters such as signal integrity with respect to clock frequency, drivers and receivers, and transmission line impedance. Design parameters such as net topology, interconnect delay, overshoot or crosstalk limits and characteristic impedance may be applied to selected nets or signals. Most importantly, a tool should allow the designer to determine the optimum parameters for the product early in the design process.
The engineer needs the ability to make realistic trade-offs to ensure that the design is routable, manufacturable, and cost effective while meeting quality standards. Concurrency is vital as placement and routing become an iterative process at best, especially with tighter space and cost constraints. Adding the additional constraints of EMI and SI analysis at the end of the process may render such designs unroutable. It is far better to constrain at the beginning than to check at the end.
A software tool designed to combat signal integrity problems should feature a simulation environment to provide extensive "what-if" scenarios, allowing the engineer to experiment with the design, change potential components, and create and assess the impact on performance quality. In the past this could only be achieved through hardware prototypes which take too long to develop, and can be difficult to analyze if more than one parameter has changed. Today, this type of testing may be accomplished in a simulation environment using software tools.
Simulation results provide the designer with a general indication of how the design will perform. This is a key element of any design flow, and signal integrity and EMI are no exception. The enabling technology for this capability comes from research at the University of Missouri at Rolla (UMR) and a number of EDA companies that focus on a new set of algorithms. Many are based on a fast radiation screening rather than using techniques such as finite element analysis or method of moments (where the currents on all conducted surfaces are computed in detail and are then used to determine the resulting fields at any point in space).
By contrast, the UMR algorithm partitions the different radiation as the result of the differential mode and the common mode noise in the design. The common mode voltage drop induces currents in structures such as heat sinks and cables creating a radiating dipole. The algorithm takes care of all these parasitic dipoles and adds them together to create the overall radiation level. The advantage is that this analysis takes minutes instead of hours for a complex design, as it is based on partitioning.
An essential feature of the design process is design management. In addition to providing a clear overview of the design at any point in the flow, a spreadsheet can provide a record of the constraints set for the design, therefore ensuring consistency throughout the project. This includes the data required for layout functions such as floorplanning and routing. It supports the popular approach taken by many board design teams today, whereby the design engineer will undertake to pre-route and analyze the critical nets, making adjustments as necessary, before the rest of the PCB is routed. Constraints can then be modified and refined by the designer, and are available for use in the next stage (physical design) of the project.
The designer also has to avoid the trap of over-constraining a design and rendering it impossible to design or build. This is where the human being is vital, and why design cannot be handled fully automatically. Engineering expertise is vital in determining the best way of achieving the design objective.
Design is not a linear flow, so having the world's most accurate point tool is of less value if it slows down the whole interactive cycle. What is more important is having the tight integration of tools to reduce that interactive cycle and at the same time, have tools that offer the best ratio of accuracy to performance. The importance of integrating EMI and signal integrity tools within the board design flow cannot be emphasized enough.
Reducing design iterations is key to meeting time to market demands. Checking out the design up front in the process is key to reducing design iterations. The integrated design environment, using consistent data and one set of constraints, facilitates the ability to move freely between design entry, verification, pre-layout and physical design. It also provides the best support for concurrent design within larger teams and between design and layout teams.
Design engineers can feel much more confident about regarding EMI and signal integrity as just another set of design constraints if they have the tools to ensure these effects are fully taken into account. It becomes just another part of the design process.
Michael Dzado is CAE Applications Engineer for the CR5000 layout system at Zuken USA.