SAN FRANCISCO A technical session at this week's Semicon West gave chip designers a look inside the development process for the low-k dielectric materials that many judge essential to progress in IC interconnect. Comparing notes were researchers from Sematech International and materials vendors, all of whom are reaching for the gauntlet thrown down by the International Technology Roadmap for Semiconductors.
The challenge envisioned by the ITRS is a continually shrinking dielectric constant for the insulating material that goes between copper interconnects in advanced chips. The low-k materials used in today's leading-edge process technologies, though with a decidedly mixed yield history, have a k-value greater than 2.6, according to Hunter Martinez, a researcher from Motorola's Semiconductor Products Sector. But by the 65-nanometer process node, the ITRS calls for a k-value in the range of 2.4, not for the dielectric material itself, but for the entire stack that makes up a chip's intermetal layers. This requires a material with an inherent k-value of around 2.2.
That, in turn, will require the use of porous materials, according to several of the speakers. The current candidates are mostly materials that when dried polymerize to leave a network of open space. In effect it is air that provides the low-k, and the polymer just keeps the mechanical structure intact.
But researchers are running into serious problems. And while there is by no means agreement on the composition of the materials, there is general agreement on the issues.
"The problem is that these materials are essentially sponges," said Martinez. "They are hard to clean, they absorb chemicals from other process steps and then they contaminate other materials."
A paper authored by Alain Cannizzaro of STMicroelectronics concisely listed the problems. According to the researcher, both the modulus and the adhesion of the new materials is substantially inferior to the characteristics of existing materials. Consequently, when subjected to the stresses of chemical-mechanical polishing, thermal stress or even cleaning, the materials tend to tear apart or separate from the metal. Because the substances are porous and relatively soft, they tend to absorb chemicals. The most pernicious result of this habit is that they tend to let captured ammonia leach out through vias, contaminating photoresist and plugging the vias with undeveloped resist. Another difficulty is that chemicals that get into the porous material displace air, and therefore increase the k of the material. One paper pointed out that contaminated low-k materials can actually have a higher k-value than the oxides they were supposed to obsolete. And the mechanical weakness of the material causes problems downstream in wire bonding and solder bump connection.
The squishiness also gives fits to chemical-mechanical polishing processes, severely limiting polishing speed and pressure, or making the step altogether impossible. Even switching to non-abrasive polishes doesn't altogether solve this problem, according to Sematech.
Researchers said that all of these problems were probably solvable. But they admitted that the industry is running behind. "We are already late in developing the materials called for in 2004 on the ITRS road map," warned Brian Daniels of Honeywell Electronic Materials. Daniels observed the irony that the only good way to decrease k with these materials is to increase the porosity of the material. That is not hard to do, Daniels said, but all of the negative characteristics of the materials increase with porosity. The problem is forming a material that is just porous enough for the necessary dielectric constant, and then learning to treat it with sufficient care.
And that's where the chip design team comes in, according to Daniels, because in the end it is chip designers, not the ITRS, who will determine the necessary value of k.
"People are learning to design around a higher k," Daniels said, "by being smart about distances of closest approach in their metal designs." Daniels suggested that improved routing algorithms and more care could keep metal runs further apart, particularly in the lateral spacing where most of the intermetal capacitance is generated, making the design less sensitive to k. By taking these pains in the design process, the team could be rewarded with elimination of some very delicate mask-and-etch operations, use of simpler materials and elimination of some serious failure modes in other words, they could get higher yields.
"Chip design must be part of the integration team," Daniels said. "Otherwise you have to be much more aggressive in your process." He suggested that integrated device manufacturers had a natural advantage in this regard, since their chip design, process design and manufacturing staffs all work under one roof, at least in theory. But the situation presents a serious problem for foundries. Having no control over how carefully their customers design for k-tolerance, they must push their processes at least to the ITRS benchmark numbers to make them robust enough to take everything the customers throw at them.