Cool beans for Xilinx
First of all, I have a couple of snippets of news with regard to the latest release of Xilinx's Integrated Software Environment (ISE 5.1i), which was officially announced on August 26.
Just to remind ourselves, an optional plug-in module called Modular Design has been available with ISE since the 3.0 release a couple of years ago. The idea behind Modular Design is that it allows you to take a large design and quickly and easily divide it into smaller portions (modules). Each module has its own timing requirements / constraints / budgets based on up-front floorplanning using estimated gate counts, and the various modules can subsequently be implemented by different teams working in parallel. Once a module is finished, it is locked back into the main floorplan, where it hangs around waiting for the other modules to be completed.
Well one new utility that's going to be made available with ISE 5.1i as an integrated (no-cost) tool is called Macro Builder. This will allow you to take an existing floorplanned design, press the "Go" button, and convert it into a placed macro. This finished macro can subsequently be archived in your internal "IP catalog" and used in future designs, and it can also be used to implement a module in Modular Design.
Another cool utility that comes integrated with ISE 5.1i is called Incremental Design, which will be of interest for anyone working on mid-to-large density projects. This little rascal allows you to use a new feature called PACE (Pin-out and Area Constraints Editor) to graphically floorplan your design along hierarchical boundaries and to graphically manage the inter-module pin locations/assignments. You can then finish the design as usual. However, if the specification of a module should mutate in such a way that it requires an HDL change, then by virtue of Incremental Design and the up-front work you performed with PACE, all you have to do is re-implement that module and the rest of the placed/routed design will remain "as-is," which sounds like "Cool Beans" to me.
Mega-cool beans for Axis
As you may have gathered from some of my recent columns, I'm quickly becoming a devotee of the concept of assertions and everything you can do with them. Until recently, however, one fly in the ointment has made itself apparent when you come to hardware acceleration/emulation. While the functional portion of the design can reside in the hardware accelerator/emulator, prior to now the assertion code has typically been obliged to run under the software simulator on the host processor, which dramatically slows things down.
Well, Axis Systems has just augmented the ReConfigurable Computing (RCC) technology that powers its Xtreme, Xtreme II, and Xcite accelerator/emulators with something called the Assertion Processor. The idea is that handling assertions can be split into two phases: detection and failure processing. This new Axis technology means that assertion detection is performed by the Assertion Processor portion of the RCC engine. Any failure triggers an interrupt, which instigates a service routine that is processed in software on the host computer (the best of both worlds really). Mapping assertions into the RCC and using this interrupt-driven approach means that there's no overhead when there aren't any assertion failures, which allows you to continue to achieve a 1000x performance advantage over software simulation.
Furthermore, this assertion-handling scheme works real well with the existing Axis VCD-on-Demand (VoD) technology. When you detect an assertion failure, one of the things you might wish to do is to look at the signals leading to this failure. The problem with hardware acceleration/emulation is that constantly storing all of the signal changes from the beginning of the simulation (a) slows things down dramatically and (b) can consume a huge amount of disk space. The idea behind VoD is to periodically take a "snapshot" of the current state of the system (which typically adds less than 5 percent overhead to the process). Then, when you detect a simulation violation, you can simply regress to the most recent snapshot and re-run from that point, but this time capturing and dumping all of the signal transitions.
Similarly, when an assertion failure is detected, the service routine associated with that assertion can also cause the system to regress to the most recent VoD snapshot, re-run from that point, and display the sequence of events leading up to the assertion violation. All of this sounds like "Mega-Cool Beans" to me!
Hurrah for Mentor, but boo for McGraw Hill
The term "Mentor" refers to a wise and trusted counselor or teacher. (This derives from Greek mythology, whereby Athena took the guise of someone called Mentor to become the guardian and teacher of Telemachus ... be honest, you don't get these nuggets of information in many EDA columns, do you?)
This may go some way to explain why the Mentor Graphics Corporation we all know and love are so enthusiastic about their higher education program, in which they make their tools available to colleges and universities around the world. Any college can apply for access to full-blown versions of all of Mentor's commercial products. There's no charge for the products themselves -- just a small maintenance fee that covers as many seats/licenses as you want. And even better, the application process is relatively simple and it doesn't take a rocket scientist to wend your weary way through a confusing maze of beauracacy.
As I pen these words, there are about 550 educational establishments taking advantage of this scheme around the world (220 of which are in North America). So all of this is jolly good, but it doesn't really help someone like myself, who is long out of college but who would love to get some "hands on" time with different tools every now and again.
So you can only imagine my surprise and delight when someone sent me a copy of something called the "Verilog Computer-Based Training Course" which promises to allow you to "Teach yourself the fastest-growing HDL -- hands down and hands on!" In addition to a small manual, this package includes a CD-ROM containing a series of self-paced tutorials. Of particular interest is the fact that Mentor (along with a number of other EDA companies) has provided special editions of some of its tools. In Mentor's case, versions of the ModelSim simulator and the Leonardo Spectrum synthesis tool were donated to the project.
That's the good news. The bad news is that the manual and tutorial materials themselves were created by a university professor (doubtless with the aid of his students) ... and it shows. The most professional part of this production is the package, which gives the impression that this is a full-blown McGraw Hill product with all that implies. However, if you open the manual on almost any page, it's obvious that no one has actually bothered to copy-edit it in any way.
For example, flicking through the manual at random as I pen these words, I learn that "Trainings are designed to cover a wide range of audience with different hardware design backgrounds," (page xii) and "After deciding what stream you want to start your study of Verilog, go to Stream 7," (page 17) where "Stream" is their name for "Tutorial," but what's the point of me deciding which one I'm interested in if I then must go to Stream 7?
And when we come to the CD itself ... the mind boggles. The graphics and animations are early 1990s on a bad day, and the whole presentation is ... well, sort of indescribable really. One can only watch in disbelief as the horror unfolds (and remember that I'm the one who always tries desperately to find something good to say about almost everything).
So where do we go from here. At $199.95, this little rapscallion would make most of our eyes water ... but when you consider the software contributions from Mentor and the other EDA companies you start to think that this is really rather a good deal ... but then you consider the pain involved in actually using the tutorial materials themselves .... arrggghhhh!
So, with a little tear rolling down my cheek (I just looked at the graphics and animations on the CD again) I'll bid you adieu ... until next time, have a good one ...