HOLLIS, N.H. An open-source tool created by an ASIC designer promises to automate the laborious process of generating Verilog code for processor registers. Developed by Chuck Benz, an independent contractor here, the tool is now available for downloading from Benz' Web site.
The tool, csrGen, is a Perl script that automatically creates the control status registers (CSRs) that handle processor read/write access in ASIC or FPGA design. Users provide information about registers and fields, and csrGen produces RTL Verilog code.
While most open-source EDA tools are offered by universities or vendors, an increasing number of tools have been developed and offered by individual engineers in recent months. These include RHDL, an HDL based on the Ruby programming language; a C-like verification language; and ChipVault, a utility that launches synthesis tools, tracks HDL files and manages hierarchy.
Benz said he came up with the idea for csrGen when he was working at Digital Equipment Corp. and revived it for his own use when he became an independent contractor. Benz has been an ASIC designer since 1983 and has been on his own for the past year and a half, working primarily in the Boston area.
"When you start writing RTL code for processor interfaces, there's a lot of redundancy," he said. "You're putting the same information down several times. It's very repetitive work that's better left to a program."
Simpler than Verilog
Compared to just writing Verilog code, Benz said, csrGen provides a simpler and terser syntax, makes it easy to quickly add new fields to registers and, perhaps most importantly, helps avoid common errors like inconsistent read and write operations.
"There was a very interesting error in some logic I bought from an IP vendor," Benz said. "We got the design in the lab and discovered two CSR bits that were swapped between read and write, so you wrote a '1,0' and ended up reading back a '0,1.'"
The tool can be adapted to any processor, Benz said, and can generate both read/write registers and read-only registers. He said there's no limit on design size. "I'm currently using it for a design with 256 addresses, and it generates 10,000 lines of Verilog code," he said.
To use csrGen, the designer creates a list of all the registers in the design and indicates the fields that go with registers for particular addresses. The designer also creates a Verilog "shell" that indicates when reads and writes occur. It's possible to declare a "sticky" bit that's cleared under specified circumstances.
Benz doesn't use the GNU Public License (GPL) that's employed for many open-source tools. "I crafted my own, much-less-restrictive license," he said. "You can distribute it freely and modify if it you want, just please leave the attribution on it."
Benz said he decided to put the tool in the public domain because "I think other people may find it useful. I've gotten to the point in my career where I like to see myself as a little bit of a mentor, someone who helps people learn more about design techniques."
Benz also has available at his Web site an open-source 8b10b encoder/decoder, a white paper on FIFOs and ring buffers, and a white paper on the use of Hamming code to protect blocks of data against single-bit errors.